公开(公告)号：US20140301134A1

公开(公告)日：2014-10-09

申请号：US13857099

申请日：2013-04-04

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally ,  John W. Poulton ,  Thomas Hastings Greer, III ,  Brucek Kurdo Khailany ,  Carl Thomas Gray

IPC: G11C7/00 ,  G11C11/41

CPC classification number: G11C7/00 ,  G11C7/1057 ,  G11C7/1069 ,  G11C11/4096 ,  G11C11/41 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.

Abstract translation: 提供用于发送信号的系统。 该系统包括第一处理单元，高速缓冲存储器和封装。 第一处理单元包括第一接地参考单端信令（GRS）接口电路，第二处理单元包括第二GRS接口电路。 高速缓冲存储器包括第三和第四GRS接口电路。 该包装包括将第一GRS接口耦合到第三GRS接口并将第二GRS接口耦合到第四GRS接口的一个或多个电迹线，其中第一GRS接口电路，第二GRS接口，第三GRS接口和 第四GRS接口电路各自被配置为通过在一个迹线和地面网络之间放电电容器来沿着一个或多个电迹线的一个迹线发送脉冲。

公开(公告)号：US20140269012A1

公开(公告)日：2014-09-18

申请号：US13938161

申请日：2013-07-09

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  John W. Poulton ,  Thomas Hastings Greer, III ,  Brucek Kurdo Khailany ,  Carl Thomas Gray

IPC: G11C11/4096

CPC classification number: G11C11/4096 ,  G11C7/1057 ,  G11C7/1069 ,  H04L25/0276

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip.

Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，系统功能芯片和被配置为包括第一处理器芯片和系统功能芯片的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令（GRS）接口电路。 系统功能芯片被配置为包括第二GRS接口电路。 在MCM封装内制造第一组电迹线，并耦合到第一GRS接口电路和第二GRS接口电路。 第一GRS接口电路和第二GRS接口电路一起提供第一处理器芯片和系统功能芯片之间的通信通道。

公开(公告)号：US20140266416A1

公开(公告)日：2014-09-18

申请号：US13946980

申请日：2013-07-19

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Brucek Kurdo Khailany ,  John W. Poulton ,  Thomas Hastings Greer, III ,  Carl Thomas Gray

IPC: H05K1/11

CPC classification number: H05K1/11 ,  H04L25/028 ,  H04L25/0292

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.

Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，第二处理器芯片和被配置为包括第一处理器芯片，第二处理器芯片和互连电路的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令（GRS）接口电路。 在MCM封装内制造的第一组电迹线，用于将第一GRS接口电路耦合到互连电路。 第二处理器芯片被配置为包括第二GRS接口电路。 在MCM封装内制造的第二组电迹线，并被配置为将第二GRS接口电路耦合到互连电路。

公开(公告)号：US20140247025A1

公开(公告)日：2014-09-04

申请号：US13783137

申请日：2013-03-01

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: G05F1/10

CPC classification number: G05F1/10 ,  H02M3/1588 ,  H02M2001/0016 ,  H02M2001/0032 ,  H02M2003/1586 ,  Y02B70/1466 ,  Y02B70/16

Abstract: A system and method are provided for regulating a voltage at a load. A target current is obtained and a number of regulator phases needed to provide the target current to a load is computed based on an efficiency characteristic of the regulator phases. The regulator phases are configured to provide the target current to the load. A multi-phase electric power conversion device comprises at least two regulator phases and a multi-phase control unit. The multi-phase control unit is configured to obtain the target current, compute the number of the regulator phases needed to provide the target current to the load based on the efficiency characteristic of the regulator phases, and configure the regulator phases to provide the target current to the load.

Abstract translation: 提供一种用于调节负载电压的系统和方法。 获得目标电流，并且基于调节器相的效率特性来计算向负载提供目标电流所需的多个调节器相位。 调节器相配置为向负载提供目标电流。 多相电力转换装置包括至少两个调节器相和多相控制单元。 多相控制单元被配置为获得目标电流，基于调节器相的效率特性来计算向负载提供目标电流所需的调节器相位的数量，并且配置调节器相位以提供目标电流 到负载。

公开(公告)号：US20140204687A1

公开(公告)日：2014-07-24

申请号：US14147411

申请日：2014-01-03

Applicant: NVIDIA Corporation

Inventor： Mahmut Ersin Sinangil ,  William J. Dally

IPC: G11C29/52

CPC classification number: G11C29/52 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  G11C2029/4402

Abstract: A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address. The access assist is applied to the at least one storage cell to perform the memory access.

Abstract translation: 提供了一种用于执行基于地址的存储器访问辅助的方法和系统。 接收用于存储器访问的地址，并且基于该地址确定对与该地址相对应的至少一个存储单元启用该访问辅助。 访问辅助被应用于至少一个存储单元以执行存储器访问。

公开(公告)号：US20140132245A1

公开(公告)日：2014-05-15

申请号：US13676021

申请日：2012-11-13

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally ,  Stephen G. Tell

IPC: G01R25/00

CPC classification number: G01R25/00

Abstract: A method and a system are provided for clock phase detection. A set of delayed versions of a first clock signal is generated. The set of delayed versions of the first clock is used to sample a second clock signal, producing a sequence of samples in a domain corresponding to the first clock signal. At least one edge indication is located within the sequence of samples.

Abstract translation: 提供了一种用于时钟相位检测的方法和系统。 产生一组第一时钟信号的延迟版本。 第一时钟的延迟版本集用于采样第二时钟信号，产生与第一时钟信号相对应的域中的采样序列。 至少一个边缘指示位于样本序列内。

公开(公告)号：US20140125393A1

公开(公告)日：2014-05-08

申请号：US14151715

申请日：2014-01-09

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  William J. Dally ,  Jonah M. Alben

IPC: H03K3/356

CPC classification number: H03K3/356 ,  H03K3/356026 ,  H03K3/356052 ,  H03K3/356147 ,  H03K3/356191

Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

Abstract translation: 本发明的一个实施例提出了一种使用向时钟信号呈现低负载的锁存电路来捕获和保持输入信号电平的技术。 时钟仅耦合到桥接晶体管和一对时钟激活的下拉或上拉晶体管。 当存储子电路未使能时，输入信号的电平被传播到输出信号。 存储子电路由桥接晶体管使能，传播子电路由一对时钟激活晶体管激活和去激活。

公开(公告)号：US10860922B2

公开(公告)日：2020-12-08

申请号：US16686931

申请日：2019-11-18

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/04 ,  G06F7/523 ,  G06N3/08

Abstract: A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. A first vector comprising only non-zero weight values and first associated positions of the non-zero weight values within a 3D space is received. A second vector comprising only non-zero input activation values and second associated positions of the non-zero input activation values within a 2D space is received. The non-zero weight values are multiplied with the non-zero input activation values, within a multiplier array, to produce a third vector of products. The first associated positions are combined with the second associated positions to produce a fourth vector of positions, where each position in the fourth vector is associated with a respective product in the third vector. The products in the third vector are transmitted to adders in an accumulator array, based on the position associated with each one of the products.

公开(公告)号：US10361023B2

公开(公告)日：2019-07-23

申请号：US14815853

申请日：2015-07-31

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Thomas Hastings Greer, III ,  Sudhir Shrikantha Kudva

IPC: H02J5/00 ,  H01F27/02 ,  H01F27/24 ,  H01F27/28 ,  H01F38/14 ,  H02J50/10

Abstract: A magnetic power supply coupling system is disclosed. An integrated circuit module includes an integrated circuit die and a secondary winding that is configured to generate an induced, alternating current based on a magnetic flux. A primary winding is external to the integrated circuit module, proximate to the integrated circuit module, and coupled to a main power supply corresponding to an alternating current that generates the magnetic flux. The induced, alternating current is converted into a direct current at a voltage level to supply power to the integrated circuit die.

公开(公告)号：US20190173380A1

公开(公告)日：2019-06-06

申请号：US16248373

申请日：2019-01-15

Applicant: NVIDIA Corporation

Inventor： Sudhir Shrikantha Kudva ,  William J. Dally ,  Thomas Hastings Greer, III ,  Carl Thomas Gray

IPC: H02M3/158 ,  H02M1/08

Abstract: A system and method are provided for controlling a modified buck converter circuit. A pull-up switching mechanism that is coupled to an upstream terminal of an inductor within a modified buck converter circuit is enabled. A load current at the output of the modified buck regulator circuit is measured. A capacitor current associated with a capacitor that is coupled to a downstream terminal of the inductor is continuously sensed and the pull-up switching mechanism is disabled when the capacitor current is greater than a sum of the load current and an enabling current value.