公开(公告)号：US10437666B2

公开(公告)日：2019-10-08

申请号：US14820396

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Nur Engin ,  Ajay Kapoor

IPC: G11C29/50 ,  G06F11/10 ,  G11C11/419 ,  G11C29/42 ,  G11C29/52 ,  G11C29/04

Abstract: In accordance with an embodiment of the invention, an IC device is disclosed. In the embodiment, the IC device includes an array of bit cells of static random-access memory (SRAM), a multi-level digitization module configured to generate a value in a range of values from a bit cell in the array of bit cells, the range of values including more than two discrete values, an output buffer configured to store the generated values, and an error correction code (ECC) decoder configured to output error corrected values based on the stored values.

公开(公告)号：US10158292B2

公开(公告)日：2018-12-18

申请号：US15412727

申请日：2017-01-23

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Steven Mark Thoen

IPC: G05F3/02 ,  H02M3/158 ,  G11C5/14 ,  H02M1/00

Abstract: As may be consistent with one or more embodiments, an apparatus and or method involves a switching power supply circuit and a control circuit therefor. The switching power supply circuit operates in high and low-power modes. In the high power mode, high and low power rails of a first circuit and of a second circuit are coupled to a power source circuit (e.g. a battery). In the low-power mode, the first circuit is operated in a high power domain and the second circuit is operated in a low power domain using recycled charge from the high power domain. The control circuit operates the switching circuit in the high-power mode and low-power mode (for power conservation) in response to a control signal.

公开(公告)号：US09960769B2

公开(公告)日：2018-05-01

申请号：US14973616

申请日：2015-12-17

Applicant: NXP B.V.

Inventor： Ajay Kapoor

IPC: H03K19/0175 ,  G06F1/26 ,  G05F3/02

CPC classification number: H03K19/017509 ,  G05F3/02 ,  G06F1/26 ,  G06F1/3296 ,  G06F11/3062 ,  G06F17/5045 ,  Y02D10/172

Abstract: One example discloses an apparatus for power management, including: a circuit having a first power-domain and a second power-domain; wherein the first and second power-domains include a set of operating parameter values; a circuit controller configured to incrementally sweep at least one of the operating parameter values of the first power-domain; a circuit profiler configured to derive a total power consumption profile of the circuit based on the circuit's response to the swept operating parameter value; wherein the circuit controller sets the operating parameter values for the first and second power-domains based on the total power consumption profile of the circuit.

公开(公告)号：US09778983B2

公开(公告)日：2017-10-03

申请号：US14820417

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Nur Engin ,  Ajay Kapoor

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/419 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C11/419 ,  G11C29/52

Abstract: An integrated circuit (IC) device including an SRAM module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ECC) encoder configured to encode input data in accordance with an ECC encoding scheme and output the encoded input data to the SRAM module, an ECC decoder configured to decode output data received from the SRAM module, output the decoded output data, and write decoding information back to the SRAM module, an error controller coupled to the ECC decoder that is configured to control the ECC decoder in accordance with the ECC encoding scheme, and a central controller coupled to the components of the wrapper logic and the SRAM module in order to control operations between the components of the wrapper logic and the SRAM module.

公开(公告)号：US09490781B2

公开(公告)日：2016-11-08

申请号：US14265097

申请日：2014-04-29

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor

IPC: H03K3/356 ,  H03K3/3562 ,  H03K3/037 ,  H03K3/012

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104 ,  H03K3/356156

Abstract: Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described.

Abstract translation: 描述锁存电路的实施例和操作锁存电路的方法。 在一个实施例中，锁存电路包括被配置为接收输入数据信号的输入端子，被配置为控制输入数据信号的应用的开关单元，连接到开关单元的第一反相器电路，其中第一反相器电路包括第一 交叉耦合对的反相器，以及通过开关单元连接到第一反相器电路的第二反相器电路。 第二逆变器电路包括第二交叉耦合的一对反相器和两个晶体管器件。 第二交叉耦合对的反相器的每个反相器通过相应的晶体管器件连接到电压轨。 两个晶体管器件中的每一个连接到开关单元与第一反相器电路或第二反相器电路之间的节点。 还描述了其它实施例。

公开(公告)号：US09417657B2

公开(公告)日：2016-08-16

申请号：US14504789

申请日：2014-10-02

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

IPC: H03K3/00 ,  G06F1/10 ,  H03K5/159 ,  H03K19/094

CPC classification number: G06F1/10 ,  H03K5/159 ,  H03K19/094

Abstract: Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.

Abstract translation: 本公开的方面涉及操作基于时间的电路。 可以结合一个或多个实施例来实现，一种装置和/或方法涉及检测在相应时钟域中工作的电路的定时特性，每个时钟域具有时钟信号路径经过的半导体主体区域。 各个半导体本体区域以各自的偏置电平被偏置，这些偏置电平是基于检测到的偏移半导体主体区域的时钟信号路径的定时特性。

公开(公告)号：US20150346742A1

公开(公告)日：2015-12-03

申请号：US14293785

申请日：2014-06-02

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Ralf Malzahn ,  Vibhu Sharma ,  Jose de Jesus Pineda de Gyvez ,  Peter Thueringer

IPC: G05F1/46

CPC classification number: G05F1/46 ,  G06F1/32

Abstract: A system including: a voltage converter configured to convert a voltage from a power source to a different voltage; a memory coupled to the voltage converter; a digital logic circuit; and a level shifter coupled between the memory and digital logic circuit; wherein leakage current from the memory is stored in a capacitance in the digital logic circuit, wherein the voltage converter is further coupled to a node between the memory and digital logic circuit, and wherein the voltage converter is configured to: monitor a voltage at the node wherein the node has a desired operating voltage value; and adjust the voltage at the node when the voltage at the node varies from the desired operating voltage value.

Abstract translation: 一种系统，包括：电压转换器，被配置为将来自电源的电压转换成不同的电压; 耦合到电压转换器的存储器; 数字逻辑电路; 以及耦合在存储器和数字逻辑电路之间的电平移位器; 其中来自所述存储器的泄漏电流被存储在所述数字逻辑电路中的电容中，其中所述电压转换器进一步耦合到所述存储器和数字逻辑电路之间的节点，并且其中所述电压转换器被配置为：监视所述节点处的电压 其中所述节点具有期望的工作电压值; 并且当节点电压从期望的工作电压值变化时调节节点处的电压。

公开(公告)号：US20150123723A1

公开(公告)日：2015-05-07

申请号：US14265097

申请日：2014-04-29

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor

IPC: H03K3/356

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104 ,  H03K3/356156

Abstract: Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described.

Abstract translation: 描述锁存电路的实施例和操作锁存电路的方法。 在一个实施例中，锁存电路包括被配置为接收输入数据信号的输入端子，被配置为控制输入数据信号的应用的开关单元，连接到开关单元的第一反相器电路，其中第一反相器电路包括第一 交叉耦合对的反相器，以及通过开关单元连接到第一反相器电路的第二反相器电路。 第二逆变器电路包括第二交叉耦合的一对反相器和两个晶体管器件。 第二交叉耦合对的反相器的每个反相器通过相应的晶体管器件连接到电压轨。 两个晶体管器件中的每一个连接到开关单元与第一反相器电路或第二反相器电路之间的节点。 还描述了其它实施例。