公开(公告)号：US11606102B2

公开(公告)日：2023-03-14

申请号：US17449030

申请日：2021-09-27

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Marcello Ganzerli ,  Pierluigi Cenci ,  Lucien Johannes Breems

IPC: H03M3/00

Abstract: A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency (fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

公开(公告)号：US20220416809A1

公开(公告)日：2022-12-29

申请号：US17449030

申请日：2021-09-27

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Marcello Ganzerli ,  Pierluigi Cenci ,  Lucien Johannes Breems

IPC: H03M3/00

Abstract: A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency(fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

公开(公告)号：US11502699B1

公开(公告)日：2022-11-15

申请号：US17357467

申请日：2021-06-24

Applicant: NXP B.V.

Inventor： Robert Rutten ,  Hendrik van der Ploeg ,  Lucien Johannes Breems ,  Martin Kessel ,  Muhammed Bolatkale ,  Bernard Burdiek ,  Manfred Zupke ,  Johannes Hubertus Antonius Brekelmans ,  Shagun Bajoria

IPC: H03M3/00

Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.

公开(公告)号：US11271585B2

公开(公告)日：2022-03-08

申请号：US17065731

申请日：2020-10-08

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Lucien Johannes Breems ,  Muhammed Bolatkale

IPC: H03M3/00

Abstract: A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

公开(公告)号：US11038522B1

公开(公告)日：2021-06-15

申请号：US16779976

申请日：2020-02-03

Applicant: NXP B.V.

Inventor： Johan Frederik Witte ,  Lucien Johannes Breems ,  Robert Rutten ,  Muhammed Bolatkale ,  Johannes Hubertus Antonius Brekelmans ,  Shagun Bajoria ,  Albertus Willibrordus Oude Essink

IPC: H03M1/06 ,  H03M3/00

Abstract: An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.

公开(公告)号：US10439634B2

公开(公告)日：2019-10-08

申请号：US15935045

申请日：2018-03-25

Applicant: NXP B.V.

Inventor： Muhammed Bolatkale ,  Lucien Johannes Breems

IPC: H03M3/00 ,  H03M1/12 ,  H03M1/00

Abstract: A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.

公开(公告)号：US10098146B2

公开(公告)日：2018-10-09

申请号：US15356451

申请日：2016-11-18

Applicant: NXP B.V.

Inventor： Jan Niehof ,  Shagun Bajoria ,  Muhammed Bolatkale ,  Robert Rutten ,  Lucien Johannes Breems ,  Johannes Hubertus Antonius Brekelmans

IPC: H04W74/00 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12 ,  H04L5/00 ,  H03M1/18

Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analog-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analog-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.

公开(公告)号：US10014878B1

公开(公告)日：2018-07-03

申请号：US15849672

申请日：2017-12-21

Applicant: NXP B.V.

Inventor： Lucien Johannes Breems ,  Muhammed Bolatkale

IPC: H03M1/06 ,  H03M3/00

Abstract: A data processor is disclosed. The data processor includes a data processing module. The data processing modules includes an input for receiving an input signal, an output for providing a quantized output signal, a combining unit configured to combine a feedback signal from the output with the input signal and a quantizer configured to provide the quantized output signal based on the combined signal. The data processor further includes a correction module configured to receive the quantized output signal, generate a full-scale digital signal based on the quantized output signal, determine a metastability error in the full-scale digital signal and provide a compensated output signal based on the quantized output signal and the determined metastability error.

公开(公告)号：US09906384B1

公开(公告)日：2018-02-27

申请号：US15275968

申请日：2016-09-26

Applicant: NXP B.V.

Inventor： Robert Rutten ,  Lucien Johannes Breems ,  Johannes Hubertus Antonius Brekelmans ,  Jan Niehof ,  Muhammed Bolatkale ,  Shagun Bajoria

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H03D3/009 ,  H04L27/3863 ,  H04L2025/0349 ,  H04L2025/03808

Abstract: Corrections are provided for mismatches between an in-phase (I) signal and a quadrature-phase (Q) signal, the I and Q signals having a first frequency band. A frequency filter circuit filters the I and Q signals to produce a filtered I and Q output with a second frequency band that is a subset of the first frequency band. Digital circuitry includes a multiple-tap correction filter having a plurality of taps and configured to generate I and Q output signals by filtering the I and Q signals according to respective sets of coefficients for the plurality of taps. A coefficient estimator generates the sets of coefficients relative to different frequency bands.