公开(公告)号：US20090285008A1

公开(公告)日：2009-11-19

申请号：US12419934

申请日：2009-04-07

申请人： Hong-Sik Jeong ,  Kwang-Jin Lee ,  Dae-Won Ha ,  Gi-Tae Jeong ,  Jung-Hyuk Lee

发明人： Hong-Sik Jeong ,  Kwang-Jin Lee ,  Dae-Won Ha ,  Gi-Tae Jeong ,  Jung-Hyuk Lee

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C8/10 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3459 ,  G11C2013/0076

摘要： A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles. Selectively pre-write verifying and writing of the received write data may include, for example, writing received write data to the selected memory cell region without pre-write verification responsive to the monitored number of read cycles being greater than a predetermined number of read cycles

摘要翻译： 监视应用于诸如可变电阻存储器件的存储器件的选定存储器位置的多个读周期。 接收要写入所选存储单元的写入数据。 基于所监视的读取周期数，对接收的写入数据进行选择性的预写入验证和写入。 选择性地预写入验证和写入所接收的写入数据可以包括例如将接收到的写入数据写入所选择的存储器单元区域，而无需预写入验证，响应于所监视的读取周期数大于预定数量的读取周期

公开(公告)号：US20080101131A1

公开(公告)日：2008-05-01

申请号：US11790146

申请日：2007-04-24

申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

IPC分类号： G11C7/06

CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

公开(公告)号：US20070064473A1

公开(公告)日：2007-03-22

申请号：US11319373

申请日：2005-12-29

申请人： Kwang-Jin Lee ,  Du-Eung Kim ,  Sang-Beom Kang ,  Woo-Yeong Cho

发明人： Kwang-Jin Lee ,  Du-Eung Kim ,  Sang-Beom Kang ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C5/145 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.

摘要翻译： 相变存储器件包括具有相变材料的存储单元，适于在编程间隔期间向存储单元提供编程电流的写入驱动器，以及用于在写入驱动器期间增强写入驱动器的电流供应容量的泵电路 编程间隔。 泵电路响应于外部控制信号在编程间隔之前被激活。

公开(公告)号：US06714038B2

公开(公告)日：2004-03-30

申请号：US10171717

申请日：2002-06-14

申请人： Byong-Kwon Lee ,  Kwang-Jin Lee

发明人： Byong-Kwon Lee ,  Kwang-Jin Lee

IPC分类号： H03K1900

CPC分类号： G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1084 ,  G11C29/14 ,  G11C29/48

摘要： An apparatus and method for controlling an input termination of a semiconductor memory device that easily detect and analyze defects, functions and reliability of the device by controlling operations of the input termination. The apparatus comprises an input termination circuit for matching an impedance of a transmission line, a control circuit for processing test commands and outputting control signals in response to said processing, and a switching circuit for selectively turning on/off the input termination circuit in response to the control signals output from the control circuit.

摘要翻译： 一种用于控制半导体存储器件的输入端接的装置和方法，其通过控制输入端子的操作来容易地检测和分析器件的缺陷，功能和可靠性。 该装置包括用于匹配传输线路的阻抗的输入终端电路，用于处理测试命令的控制电路并响应于所述处理输出控制信号;以及切换电路，用于响应于所述输入终端电路选择性地接通/ 控制信号从控制电路输出。

公开(公告)号：US09034189B2

公开(公告)日：2015-05-19

申请号：US14114840

申请日：2012-06-21

申请人： Jae Hee Ryu ,  Yong-Cheol Shin ,  Kwang-Jin Lee ,  Moo-Seok Lee

发明人： Jae Hee Ryu ,  Yong-Cheol Shin ,  Kwang-Jin Lee ,  Moo-Seok Lee

IPC分类号： B01D63/04 ,  B01D69/08 ,  B01D69/12 ,  B01D71/68 ,  B01D71/34 ,  B01D71/48 ,  B01D63/02 ,  B01D69/10

CPC分类号： B01D63/04 ,  B01D63/021 ,  B01D63/027 ,  B01D69/08 ,  B01D69/10 ,  B01D69/12 ,  B01D71/34 ,  B01D71/48 ,  B01D71/68 ,  B01D2313/23 ,  B01D2325/40

摘要： Disclosed is a pressurized hollow fiber membrane module that exhibits improved durability without deterioration in packing density and permeation flux. The pressurized hollow fiber membrane module includes a composite hollow fiber membrane comprising a tubular braid woven by yarns and a polymer film on the outer surface of the tubular braid. At least one of the yarns comprises a small-fineness filament and a medium-fineness filament. The small-fineness filament comprises first monofilaments having a fineness of 0.01 to 0.4 denier, the medium-fineness filament comprises second monofilaments having a fineness higher than 0.4 and lower than 3, and a ratio of thickness of the tubular braid to outer diameter thereof is 15 to 35%.

摘要翻译： 公开了一种加压中空纤维膜组件，其具有改善的耐久性，而不会降低填充密度和渗透通量。 加压中空纤维膜组件包括复合中空纤维膜，其包括由纱线编织的管状编织物和在管状编织物的外表面上的聚合物膜。 至少一根纱线包括细细丝和中细丝。 小细丝包括细度为0.01至0.4旦尼尔的第一单丝，中细丝包括细度高于0.4且低于3的第二单丝，并且管状编织物的厚度与外径之比为 15到35％。

公开(公告)号：US20120090641A1

公开(公告)日：2012-04-19

申请号：US13265148

申请日：2010-04-19

申请人： Kwang-Jin Lee

发明人： Kwang-Jin Lee

IPC分类号： B01D65/06 ,  B08B5/00 ,  B08B9/00 ,  B08B3/08

CPC分类号： B01D65/02 ,  B01D63/02 ,  B01D2315/06 ,  B01D2321/04 ,  B01D2321/162 ,  B01D2321/168 ,  B01D2321/185

摘要： A method for cleaning a filtering membrane, contaminated by contaminants including inorganic and organic materials during a fluid-filtering process, is disclosed, the method comprises cleaning the filtering membrane by using a first cleaning solution of pH 6˜9 so as to remove the organic material from the filtering membrane; and cleaning the filtering membrane by using a second acid cleaning solution so as to remove the inorganic material from the filtering membrane, wherein the cleaning method of the present invention uses the first cleaning solution having pH 6˜9 instead of a strong-alkaline cleaning solution so as to prevent the filtering membrane from being damaged, and also uses the cleaning solution maintained at a a relatively low temperature instead of hot water so as to improve economical efficiency by reduction of energy consumption.

摘要翻译： 公开了一种在流体过滤过程中清洁被污染物包括无机和有机材料的过滤膜的方法，该方法包括使用pH6〜9的第一清洗液清洗过滤膜，以除去有机物 过滤膜材料; 并使用第二酸洗液清洗过滤膜，以从过滤膜中除去无机材料，其中本发明的清洗方法使用pH6〜9的第一清洗液代替强碱性清洗液 以防止过滤膜损坏，并且还使用保持在较低温度的清洗溶液代替热水，从而通过降低能量消耗来提高经济性。

公开(公告)号：US20110209030A1

公开(公告)日：2011-08-25

申请号：US13099640

申请日：2011-05-03

申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

摘要翻译： 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。

公开(公告)号：US20100302884A1

公开(公告)日：2010-12-02

申请号：US12662247

申请日：2010-04-07

申请人： Kwang-Jin Lee ,  Yong-Jun Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Joon-Yong Choi

发明人： Kwang-Jin Lee ,  Yong-Jun Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Joon-Yong Choi

IPC分类号： G11C7/00

CPC分类号： G11C7/04 ,  G11C7/18 ,  G11C7/22 ,  G11C16/32 ,  G11C2207/002

摘要： Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a read operation signal a check result is generated. The write operation signal is modified based on the check result.

摘要翻译： 公开了一种防止用于非易失性半导体存储器件的耦合噪声的方法。 根据该方法，如果写入操作信号的边缘与读取操作信号的激活时段重叠，则产生检查结果。 基于检查结果修改写操作信号。

公开(公告)号：US07751232B2

公开(公告)日：2010-07-06

申请号：US11953146

申请日：2007-12-10

申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/08 ,  G11C13/0004

摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US07535760B2

公开(公告)日：2009-05-19

申请号：US11902424

申请日：2007-09-21

申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

IPC分类号： G11C14/00

CPC分类号： H01L27/10802 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4063 ,  H01L21/84 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.

摘要翻译： 公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。 非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器 对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。