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91 条记录 (耗时 0.029 秒)

    Symbol Flipping Data Processor
    31.
    发明申请
    Symbol Flipping Data Processor 有权
    符号翻转数据处理器

    公开(公告)号：US20130198580A1

    公开(公告)日：2013-08-01

    申请号：US13363751

    申请日：2012-02-01

    申请人： Lei Chen ,  Haitao Xia ,  Ming Jin ,  Johnson Yen

    发明人： Lei Chen ,  Haitao Xia ,  Ming Jin ,  Johnson Yen

    IPC分类号： G06F11/07 ,  H03M13/09 ,  G06F11/10 ,  H03M13/05

    CPC分类号： G11B20/1833 ,  G06F11/1076 ,  G11B2020/185 ,  G11B2020/1859 ,  H03M13/1108 ,  H03M13/1128 ,  H03M13/1171 ,  H03M13/2951 ,  H03M13/2957 ,  H03M13/6331 ,  H03M13/6343

    摘要： Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector.

    摘要翻译： 本发明的各种实施例提供了一种符号翻转数据处理器的系统和方法。 例如，公开了一种符号翻转数据处理器，其包括可操作以执行错误校验计算的符号翻转数据处理器中的数据解码器，以及符号翻转数据处理器中的数据检测器，可操作以至少至少在数据检测器中执行符号翻转 部分地基于错误检查计算，其中数据处理器的输出至少部分地基于数据检测器中的符号翻转而被产生。

    Systems and Methods for SNR Measurement Using Equalized Data
    33.
    发明申请
    Systems and Methods for SNR Measurement Using Equalized Data 有权
    使用均衡数据进行SNR测量的系统和方法

    公开(公告)号：US20130148233A1

    公开(公告)日：2013-06-13

    申请号：US13316953

    申请日：2011-12-12

    申请人： Haitao Xia ,  Ming Jin ,  Dahua Qin ,  Shaohua Yang

    发明人： Haitao Xia ,  Ming Jin ,  Dahua Qin ,  Shaohua Yang

    IPC分类号： H03H7/30 ,  G11B5/035

    CPC分类号： G11B5/59605 ,  G11B5/035 ,  G11B5/09 ,  G11B5/59622 ,  G11B20/10046 ,  G11B2220/415

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an equalizer circuit, a signal to noise ratio calculation circuit, and a parameter adjustment circuit. The equalizer circuit is operable to equalize a data input to yield an equalized output. The signal to noise ratio calculation circuit is operable to calculate a signal to noise ratio of the equalized output based at least in part on a noise power derived from the equalized output. The parameter adjustment circuit is operable to adjust a parameter based at least in part on the signal to noise ratio.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了包括均衡器电路，信噪比计算电路和参数调整电路的数据处理系统。 均衡器电路可操作以均衡数据输入以产生均衡的输出。 信噪比计算电路可用于至少部分地基于从均衡输出得到的噪声功率来计算均衡输出的信噪比。 参数调整电路可操作以至少部分地基于信噪比来调整参数。

    Systems and Methods for Parity Sharing Data Processing
    34.
    发明申请
    Systems and Methods for Parity Sharing Data Processing 有权
    系统与方法的平等共享数据处理

    公开(公告)号：US20130091397A1

    公开(公告)日：2013-04-11

    申请号：US13269832

    申请日：2011-10-10

    申请人： Haitao Xia ,  Shaohua Yan ,  Johnson Yen

    发明人： Haitao Xia ,  Shaohua Yan ,  Johnson Yen

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/1102 ,  G11B20/1833 ,  G11B2020/185 ,  G11B2220/2516 ,  H03M13/2942 ,  H03M13/3761 ,  H03M13/6331 ,  H03M13/6343 ,  H03M13/6502

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a low density parity check data decoder circuit, and a processing circuit. The processing circuit is operable to: reconstitute a second encoded sub-codeword from a combination of data including the first encoded sub-codeword and the composite sub-codeword; and correct an error in one of the first encoded sub-codeword and the second encoded sub-codeword based at least in part on a combination of the first encoded sub-codeword, the second encoded sub-codeword, and the composite sub-codeword.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，公开了一种数据处理系统，其包括：数据检测器电路，低密度奇偶校验数据解码器电路和处理电路。 所述处理电路可操作用于：从包括所述第一编码子码字和所述复合子码字的数据的组合重构第二编码子码字; 以及至少部分地基于所述第一编码子码字，所述第二编码子码字和所述合成子码字的组合来校正所述第一编码子码字和所述第二编码子码字之一中的错误。

    Systems and Methods for Qualitative Media Defect Determination
    36.
    发明申请
    Systems and Methods for Qualitative Media Defect Determination 有权
    定性介质缺陷测定的系统和方法

    公开(公告)号：US20130047058A1

    公开(公告)日：2013-02-21

    申请号：US13213789

    申请日：2011-08-19

    申请人： Ming Jin ,  Haitao Xia ,  Lei Chen

    发明人： Ming Jin ,  Haitao Xia ,  Lei Chen

    IPC分类号： H03M13/09 ,  G06F11/07

    CPC分类号： H03M13/3746 ,  G06F11/0751 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/41 ,  H03M13/612 ,  H03M13/6331

    摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a media defect detector circuit. The media defect detector circuit is operable to compare a data input derived from a medium against at least a first defect level to yield a first level output, and a second defect level to yield a second level output; and provide a combination of the first level output and the second level output as a defect quality output. A value of the defect quality output corresponds to a likelihood of a defect of the medium.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，公开了包括介质缺陷检测器电路的数据处理电路。 介质缺陷检测器电路可操作以将从介质导出的数据输入与至少第一缺陷级别进行比较以产生第一级输出，以及产生第二缺陷电平以产生第二电平输出; 并且提供第一电平输出和第二电平输出的组合作为缺陷质量输出。 缺陷质量输出的值对应于介质缺陷的可能性。

    Systems and Methods for ADC Based Timing and Gain Control
    37.
    发明申请
    Systems and Methods for ADC Based Timing and Gain Control 有权
    基于ADC的时序和增益控制的系统和方法

    公开(公告)号：US20130021187A1

    公开(公告)日：2013-01-24

    申请号：US13186267

    申请日：2011-07-19

    申请人： Haitao Xia ,  George Mathew ,  Shaohua Yang

    发明人： Haitao Xia ,  George Mathew ,  Shaohua Yang

    IPC分类号： H03M1/12

    CPC分类号： H03M1/1028 ,  H03M1/12

    摘要： Various embodiments of the present invention provide circuits, systems and methods for data processing. For example, a data processing circuit is discussed that includes: an analog to digital converter circuit, a target response circuit, and a timing circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples synchronous to a sampling phase. The sampling phase corresponds to a phase feedback. The target response circuit is operable to provide an expected output corresponding to a known input. The timing circuit is operable to generate the phase feedback based at least in part on values derived from the expected output.

    摘要翻译： 本发明的各种实施例提供用于数据处理的电路，系统和方法。 例如，讨论了一种数据处理电路，其包括：模数转换器电路，目标响应电路和定时电路。 模数转换器电路可操作以接收数据输入并提供与采样相位同步的相应数字采样。 采样相位对应于相位反馈。 目标响应电路可操作以提供对应于已知输入的预期输出。 定时电路可操作以至少部分地基于从预期输出导出的值来产生相位反馈。

    Systems and methods for mitigating stubborn errors in a data processing system
    40.
    发明授权
    Systems and methods for mitigating stubborn errors in a data processing system 有权
    减轻数据处理系统中顽固错误的系统和方法

    公开(公告)号：US08819527B2

    公开(公告)日：2014-08-26

    申请号：US13186234

    申请日：2011-07-19

    申请人： Haitao Xia ,  Wu Chang ,  Shaohua Yang

    发明人： Haitao Xia ,  Wu Chang ,  Shaohua Yang

    IPC分类号： H03M13/03 ,  H03M13/11 ,  H03M13/15 ,  H03M13/29 ,  H03M13/37 ,  H03M13/41 ,  H03M13/39 ,  H03M13/45 ,  H03M13/00

    CPC分类号： H03M13/1102 ,  H03M13/1515 ,  H03M13/2957 ,  H03M13/3746 ,  H03M13/41 ,  H03M13/42 ,  H03M13/451 ,  H03M13/458 ,  H03M13/6331

    摘要： Various embodiments of the present invention provide data processing circuits that include: a data detector circuit, a data decoder circuit, and a modification circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a decode input to yield a decoded output. The decode input is selected between at least the detected output, and a modified version of the detected output. The modification circuit is operable to receive the detected output and to provide the modified version of the detected output.

    摘要翻译： 本发明的各种实施例提供数据处理电路，其包括：数据检测器电路，数据解码器电路和修改电路。 数据检测器电路可操作以将数据检测算法应用于数据输入以产生检测到的输出。 数据解码器电路可操作以将数据解码算法应用于解码输入以产生解码输出。 在至少检测到的输出和检测到的输出的修改版本之间选择解码输入。 修改电路可操作以接收所检测的输出并提供所检测输出的修改版本。