公开(公告)号：US08513099B2

公开(公告)日：2013-08-20

申请号：US12817733

申请日：2010-06-17

Applicant: Josephine B. Chang ,  Paul Chang ,  Vijay Narayanan ,  Jeffrey W. Sleight

Inventor： Josephine B. Chang ,  Paul Chang ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L51/0545 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0012 ,  H01L51/0048 ,  H01L51/0525

Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.

Abstract translation: 提供了一种形成自对准器件的方法，包括将碳纳米管（CNT）沉积到晶体介质衬底上，隔离包含CNT位置的晶体介质衬底的一部分，在栅极电介质层和栅电极栅叠层 CNT同时保持其结构完整性，并且形成外延源极和漏极区域，其与从栅极介电层和栅电极栅极叠层暴露的晶体介质衬底上的CNT的部分接触。

公开(公告)号：US08472239B2

公开(公告)日：2013-06-25

申请号：US13467126

申请日：2012-05-09

Applicant: Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

Inventor： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC: G11C11/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

公开(公告)号：US08395220B2

公开(公告)日：2013-03-12

申请号：US13417829

申请日：2012-03-12

Applicant: Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

Inventor： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC: H01L27/088 ,  B82Y99/00

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  Y10S977/938

Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

Abstract translation: 提供基于纳米线的设备。 在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。 每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。 每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。

公开(公告)号：US20120227019A1

公开(公告)日：2012-09-06

申请号：US13471789

申请日：2012-05-15

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F17/50

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract translation: 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US20120217479A1

公开(公告)日：2012-08-30

申请号：US13467126

申请日：2012-05-09

Applicant: Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

Inventor： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC: H01L29/775 ,  B82Y99/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

Abstract translation: 提供了基于纳米线的场效应晶体管（FET）及其制造技术。 在一个方面，提供了一种FET，其具有在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个 的器件层被配置为具有来自一个或多个其它器件层的不同阈值电压; 以及围绕纳米线通道的每个器件层共用的栅极。

公开(公告)号：US20110279075A1

公开(公告)日：2011-11-17

申请号：US13194589

申请日：2011-07-29

Applicant: Paul Chang ,  Tsair-Rong Chen ,  Jeen-Sheen Row ,  Chin-Sheng Lu

Inventor： Paul Chang ,  Tsair-Rong Chen ,  Jeen-Sheen Row ,  Chin-Sheng Lu

IPC: H02P23/04

CPC classification number: H02P23/04

Abstract: In a method and module for controlling rotation of a motorized spindle driven by a driving unit, a sensing unit senses vibration of the spindle and generates a voltage signal corresponding to the vibration of the spindle. A processing unit receives the voltage signal from the sensing unit, generates an adjusting ratio equal to a reference voltage corresponding to a predetermined vibration level of the spindle by the voltage signal upon detecting that the voltage signal is greater than the reference voltage and is less than a predetermined threshold voltage that is greater than the reference voltage, and outputs a control signal corresponding to the adjusting ratio to the driving unit such that the driving unit reduces a rotation speed of the spindle by the adjusting ratio in response to the control signal from the processing unit.

Abstract translation: 在用于控制由驱动单元驱动的电动主轴的旋转的方法和模块中，感测单元感测主轴的振动并产生对应于主轴的振动的电压信号。 处理单元从感测单元接收电压信号，当检测到电压信号大于参考电压时，产生等于与主轴的预定振动水平相对应的参考电压的调整比例，并且小于参考电压 大于参考电压的预定阈值电压，并将与调节比相对应的控制信号输出到驱动单元，使得驱动单元响应于来自控制信号的控制信号而减小主轴的转速通过调节比 处理单元。

公开(公告)号：US20110097329A1

公开(公告)日：2011-04-28

申请号：US12822995

申请日：2010-06-24

Applicant: Paul Chang ,  Sejal Vyas ,  Anthony Leung ,  Phillip A. Sharp

Inventor： Paul Chang ,  Sejal Vyas ,  Anthony Leung ,  Phillip A. Sharp

IPC: A61K39/395 ,  C12N5/02 ,  A61P35/00 ,  C12Q1/48 ,  C12Q1/68

CPC classification number: C12N15/1137 ,  A61K31/713 ,  A61K38/45 ,  A61K38/47 ,  A61K39/395 ,  A61K39/3955 ,  C07H21/02 ,  C07K16/40 ,  C12N15/113 ,  C12N2310/14 ,  C12N2320/12 ,  C12Q1/6886 ,  G01N33/6893 ,  G01N2333/91142 ,  G01N2500/02

Abstract: The invention provides methods for treating or decreasing the likelihood of developing a stress-granule related disorder and/or cancer by administering one or more poly-ADP-ribose polymerase (PARP) inhibitors, one or more PARP activators, one or more poly-ADP-ribose glycosylase (PARG) activators, and/or one or more poly-ADP-ribose glycohydrolase ARH3 activators. The invention also provides corresponding methods of decreasing stress granule formation and/or proliferation in a cell or a population of cells. The invention further provides methods of increasing the number of stress granules and proliferation in a cell or a population of cells by administering one or more PARP activators, one or more PARP inhibitors, one or more PARG inhibitors, and/or one or more ARH3 inhibitors. The invention also provides methods for screening for agents for treating or decreasing the likelihood of developing a stress granule-related disorder or cancer, and methods for determining the propensity for developing a stress granule-related disorder or cancer, as well as compositions and kits containing one or more PARP inhibitors, one or more PARP activators, one or more PARG activators, and one or more ARH3 activators.

Abstract translation: 本发明提供了通过施用一种或多种聚ADP-核糖聚合酶（PARP）抑制剂，一种或多种PARP激活剂，一种或多种聚ADP来治疗或降低发展应激颗粒相关病症和/或癌症的可能性的方法 核糖糖酵解酶（PARG）激活剂和/或一种或多种聚ADP-核糖糖水解酶ARH3激活剂。 本发明还提供减少细胞或细胞群体中应激颗粒形成和/或增殖的相应方法。 本发明还提供了通过施用一种或多种PARP激活剂，一种或多种PARP抑制剂，一种或多种PARG抑制剂和/或一种或多种ARH3抑制剂来增加细胞或细胞群体中的应激颗粒数量和增殖的方法 。 本发明还提供筛选用于治疗或降低发展应激颗粒相关病症或癌症的可能性的药剂的方法，以及用于确定发展应激颗粒相关病症或癌症倾向的方法，以及含有 一种或多种PARP抑制剂，一种或多种PARP活化剂，一种或多种PARG活化剂和一种或多种ARH3活化剂。

公开(公告)号：US20100297816A1

公开(公告)日：2010-11-25

申请号：US12848582

申请日：2010-08-02

Applicant: Stephen W. Bedell ,  Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

Inventor： Stephen W. Bedell ,  Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

IPC: H01L21/336

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  Y10S977/72 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/938

Abstract: A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.

Abstract translation: 提供一种半导体结构，其包括位于衬底表面上的多个垂直堆叠且垂直间隔开的半导体纳米线（例如，半导体纳米线网）。 每个垂直堆叠和垂直间隔开的半导体纳米线的一个端段连接到源极区域，并且每个垂直堆叠和垂直间隔开的半导体纳米线的另一个端部段连接到漏极区域。 包括栅极电介质和栅极导体的栅极区域邻接多个垂直堆叠和垂直间隔的半导体纳米线，并且源极区域和漏极区域与栅极区域自对准。

公开(公告)号：US07610472B2

公开(公告)日：2009-10-27

申请号：US11422325

申请日：2006-06-05

Applicant: Hyeonkuk Jeong ,  Paul Chang

Inventor： Hyeonkuk Jeong ,  Paul Chang

IPC: G06F9/315

CPC classification number: G06F5/01 ,  G06F9/30032 ,  G06F9/3017

Abstract: Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The method simulates a shift instruction that shifts an operand by a shift count. The method identifies a first shift command and a second shift command. The method computes a mask value. The mask value depends on whether the shift count is less than half of the operand size or greater than or equal to half of the operand size. The method uses the mask value to cause one of the first shift command and the second shift command to produce no shift. In some embodiments, the method allows for the shift count to be specified in bytes or in bits.

Abstract translation: 一些实施例提出了执行可变移位操作的方法。 该方法可以由微处理器使用，该微处理器不允许某些操作数大小进行可变移位操作。 该方法模拟一个将一个操作数移位一个移位计数的移位指令。 该方法识别第一移位指令和第二移位指令。 该方法计算一个掩码值。 掩码值取决于移位计数是否小于操作数大小的一半，或大于或等于操作数大小的一半。 该方法使用掩模值使第一移位指令和第二移位指令之一产生无移位。 在一些实施例中，该方法允许以字节或位指定移位计数。

公开(公告)号：US20090245961A1

公开(公告)日：2009-10-01

申请号：US12060460

申请日：2008-04-01

Applicant: Paul Chang ,  Tsair-Rong Chen ,  Jeen-Sheen Row ,  Yuan-Fu Tsai

Inventor： Paul Chang ,  Tsair-Rong Chen ,  Jeen-Sheen Row ,  Yuan-Fu Tsai

IPC: B23C9/00

CPC classification number: B23C1/002 ,  B23Q1/66 ,  Y10T409/305264 ,  Y10T409/308288 ,  Y10T409/309576

Abstract: A machining apparatus includes a support frame, first and second workbenches, and a tool-mounting unit. The support frame includes a first horizontal frame part, and a second horizontal frame part disposed above the first horizontal frame part. The first and second workbenches are mounted slidably on the first horizontal frame part of the support frame, and is slidable relative to the support frame in a first horizontal direction. The tool-mounting unit is mounted slidably on the second horizontal frame part of the support frame, and is slidable relative to the support frame in a second horizontal direction transverse to the first horizontal direction.

Abstract translation: 一种加工装置，包括支撑框架，第一和第二工作台以及工具安装单元。 支撑框架包括第一水平框架部分和设置在第一水平框架部分上方的第二水平框架部分。 第一和第二工作台可滑动地安装在支撑框架的第一水平框架部分上，并且可在第一水平方向上相对于支撑框架滑动。 工具安装单元可滑动地安装在支撑框架的第二水平框架部分上，并且能够在横向于第一水平方向的第二水平方向上相对于支撑框架滑动。