公开(公告)号：US20100090264A1

公开(公告)日：2010-04-15

申请号：US12249060

申请日：2008-10-10

申请人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

发明人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

摘要翻译： 一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。 互连件包括布置在半导体本体表面下方的金属体。 接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。 接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。 还公开了其它方法，装置和系统。

公开(公告)号：US20070161277A1

公开(公告)日：2007-07-12

申请号：US11678735

申请日：2007-02-26

申请人： Peter Baars ,  Klaus Muemmler ,  Daniel Koehler

发明人： Peter Baars ,  Klaus Muemmler ,  Daniel Koehler

IPC分类号： H01R29/00

CPC分类号： H01L28/91 ,  H01L21/76816 ,  H01L27/10817 ,  H01L27/10894

摘要： A memory device includes an array of memory cells and a storage capacitor for storing information. Each memory cell includes an access transistor. The access transistor includes first and second source/drain regions, a channel disposed between the first and the second source/drain regions, and a gate electrode electrically insulated from the channel and adapted to control the conductivity of the channel. The access transistor is at least partially formed in the semiconductor substrate. The storage capacitor is adapted to be accessed by the access transistor. The storage capacitor includes at least first and second storage electrodes and at least a capacitor dielectric disposed between the first and the second storage electrodes. Each of the first and the second storage electrodes is disposed above the substrate surface.

摘要翻译： 存储器件包括存储单元阵列和用于存储信息的存储电容器。 每个存储单元包括存取晶体管。 存取晶体管包括第一和第二源极/漏极区域，设置在第一和第二源极/漏极区域之间的沟道以及与沟道电绝缘并适于控制沟道的导电性的栅电极。 存取晶体管至少部分地形成在半导体衬底中。 存储电容适于由存取晶体管访问。 存储电容器至少包括第一和第二存储电极以及设置在第一和第二存储电极之间的至少一个电容器电介质。 第一和第二存储电极中的每一个设置在基板表面上方。

公开(公告)号：US20080111174A1

公开(公告)日：2008-05-15

申请号：US11559563

申请日：2006-11-14

申请人： Peter Baars ,  Klaus Muemmler

发明人： Peter Baars ,  Klaus Muemmler

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/105 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897

摘要： A memory device comprises an array of memory cells, the memory cells being at least partially formed in a semiconductor substrate having a surface, each of the memory cells including an access transistor and a storage capacitor for storing data, the storage capacitor including a first and a second capacitor electrodes and a capacitor dielectric disposed between the first and second capacitor electrodes. The first capacitor electrode extends to a first electrode height. The memory device also includes a peripheral portion including peripheral circuitry and a wiring layer. The wiring layer includes first lines, wherein a bottom surface of each of the first lines is disposed at a bottom surface height which is greater than 0.25 times the first electrode height, and each of the first lines has a line thickness less than 200 nm.

摘要翻译： 存储器件包括存储器单元阵列，存储器单元至少部分地形成在具有表面的半导体衬底中，每个存储单元包括存取晶体管和用于存储数据的存储电容器，所述存储电容器包括第一和 设置在第一和第二电容器电极之间的第二电容器电极和电容器电介质。 第一电容器电极延伸到第一电极高度。 存储装置还包括包括外围电路和布线层的周边部分。 所述布线层包括第一线，其中，所述第一线的底面设置在大于所述第一电极高度的0.25倍的底面高度，并且所述第一线的线条厚度小于200nm。

公开(公告)号：US07687343B2

公开(公告)日：2010-03-30

申请号：US11633090

申请日：2006-12-04

申请人： Peter Moll ,  Peter Baars ,  Till Schloesser ,  Rolf Weis ,  Klaus Muemmler

发明人： Peter Moll ,  Peter Baars ,  Till Schloesser ,  Rolf Weis ,  Klaus Muemmler

IPC分类号： H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897

摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.

摘要翻译： 存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。 第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。 每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。 存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。 存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。 绝缘层的下侧设置在第一电容器部分的上侧的高度处。

公开(公告)号：US20080128773A1

公开(公告)日：2008-06-05

申请号：US11633090

申请日：2006-12-04

申请人： Peter Moll ,  Peter Baars ,  Till Schloesser ,  Rolf Weis ,  Klaus Muemmler

发明人： Peter Moll ,  Peter Baars ,  Till Schloesser ,  Rolf Weis ,  Klaus Muemmler

IPC分类号： H01L27/108

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897

摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.

摘要翻译： 存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。 第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。 每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。 存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。 存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。 绝缘层的下侧设置在第一电容器部分的上侧的高度处。

公开(公告)号：US07374992B2

公开(公告)日：2008-05-20

申请号：US11443602

申请日：2006-05-31

申请人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

发明人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

IPC分类号： H01L21/8234

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly removing said first and second protective layer in order to bring said first and second protective layer to about a same upper level; removing said first protective layer from said first contact hole; forming at least one another contact hole in said peripheral device region, said at least one another contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one another contact hole with a respective contact plug.

摘要翻译： 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在存储单元区域中具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔; 在所述存储单元区域和外围设备区域上沉积第一保护层; 将所述至少一个栅极堆叠的所述盖暴露在所述外围设备区域中; 在处理步骤中修改所述外围设备区域中的所述至少一个栅极堆叠的所述暴露的盖，其中所述第一保护层用作所述存储单元区域中的掩模; 在所述外围设备区域中的所述修改的盖上形成第二保护层; 部分地去除所述第一和第二保护层，以便使所述第一和第二保护层大致相同的上层; 从所述第一接触孔去除所述第一保护层; 在所述外围设备区域中形成至少另一个接触孔，所述至少另一个接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或所述栅极叠层中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少另一个接触孔。

公开(公告)号：US08138538B2

公开(公告)日：2012-03-20

申请号：US12249060

申请日：2008-10-10

申请人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

发明人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

IPC分类号： H01L27/108

CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

摘要翻译： 一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。 互连件包括布置在半导体本体表面下方的金属体。 接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。 接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。 还公开了其它方法，装置和系统。

公开(公告)号：US20070281416A1

公开(公告)日：2007-12-06

申请号：US11443602

申请日：2006-05-31

申请人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

发明人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

IPC分类号： H01L21/8244

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly removing said first and second protective layer in order to bring said first and second protective layer to about a same upper level; removing said first protective layer from said first contact hole; forming at least one another contact hole in said peripheral device region, said at least one another contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one another contact hole with a respective contact plug.

摘要翻译： 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在存储单元区域中具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔; 在所述存储单元区域和外围设备区域上沉积第一保护层; 将所述至少一个栅极堆叠的所述盖暴露在所述外围设备区域中; 在处理步骤中修改所述外围设备区域中的所述至少一个栅极堆叠的所述暴露的盖，其中所述第一保护层用作所述存储单元区域中的掩模; 在所述外围设备区域中的所述修改的盖上形成第二保护层; 部分地去除所述第一和第二保护层，以便使所述第一和第二保护层大致相同的上层; 从所述第一接触孔去除所述第一保护层; 在所述外围设备区域中形成至少另一个接触孔，所述至少另一个接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或所述栅极叠层中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少另一个接触孔。

公开(公告)号：US20070253233A1

公开(公告)日：2007-11-01

申请号：US11393363

申请日：2006-03-30

申请人： Torsten Mueller ,  Peter Baars ,  Klaus Muemmler ,  Joern Regul ,  Christian Kapteyn

发明人： Torsten Mueller ,  Peter Baars ,  Klaus Muemmler ,  Joern Regul ,  Christian Kapteyn

IPC分类号： G11C5/02

CPC分类号： H01L27/115 ,  G11C5/063 ,  G11C7/18 ,  G11C8/14 ,  H01L27/11568

摘要： A device includes an array of memory cells, which are arranged vertically to a main substrate surface. The array is provided with lower bitlines, wordlines and upper bitlines. The lower and upper bitlines are contact-connected to lower source/drain regions and corresponding upper source/drain regions, respectively, in such a manner that a unique addressing of individual memory cells is possible.

摘要翻译： 一种器件包括垂直于主衬底表面布置的存储器单元阵列。 阵列设有较低位线，字线和高位线。 下位线和上位线分别以这样的方式接触连接到下源极/漏极区域和对应的上部源极/漏极区域，使得各个存储器单元的独特寻址是可能的。

公开(公告)号：US20080150012A1

公开(公告)日：2008-06-26

申请号：US12042822

申请日：2008-03-05

申请人： Andreas Thies ,  Klaus Muemmler

发明人： Andreas Thies ,  Klaus Muemmler

IPC分类号： H01L27/088

CPC分类号： H01L27/10885 ,  G11C7/02 ,  G11C7/18 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10891 ,  Y10S257/905

摘要： A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

摘要翻译： 提供了一种用于半导体存储器件的晶体管阵列。 从半导体衬底的本体部分向外延伸的多个半导体柱以行和列布置。 每个柱形成垂直通道存取晶体管的有源区。 绝缘沟槽形成在支柱之间。 掩埋字线沿绝缘沟槽沿支柱排延伸。 位线槽形成在柱柱之间。 位线在位线沟槽的下部垂直于字线延伸。 柱子的第一列和第二列面对每个位线。 每个位线经由由多晶硅形成的单面位线接触件耦合到第一柱柱的支柱中的有源区域，并且与第二柱柱的柱的有源区域绝缘。