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公开(公告)号：US20120260117A1
公开(公告)日：2012-10-11
申请号：US13079842
申请日：2011-04-05
申请人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
发明人： Emrah Acar , Pradip Bose , Bishop C. Brock , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez , Gregory S. Still
IPC分类号： G06F1/28
CPC分类号： G06F1/3243 , Y02D10/152
摘要： A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.
摘要翻译： 提供了一种自动调整电源代理架构的机制。 基于与在微处理器核心上执行的应用有关的一组条件，识别用于针对微处理器核心的一组活动中的每个活动的权重因子，从而形成一组权重因子。 使用一组活动和一组权重因子生成用电量估计值。 确定功率使用估计值是否大于识别微处理器核的最大功率使用的功率代理阈值。 响应于功率使用估计值大于功率代理阈值，一组信号被发送到与微处理器核心相关联的功率代理单元中的一个或多个片上致动器，以及与该组件相关联的一组操作参数 被调整。
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公开(公告)号：US08261276B2
公开(公告)日：2012-09-04
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译： 一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。 为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。 说明性实施例确定了处理器的目标功率效率模式。 一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。
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公开(公告)号：US20120119717A1
公开(公告)日：2012-05-17
申请号：US12944392
申请日：2010-11-11
IPC分类号： G05F1/10
摘要： Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node.
摘要翻译： 提供电源门控或旁路电压调节器的机制。 响应于接收到被断言的电源门信号以对所述电压调节器的输出电压进行电源门控，第一控制电路电源的至少一个功率门是第一电路或第二控制电路电路的输出电压门控第二电路的输出电压，使得 基本上没有电压被第一电路输出到主输出节点。 响应于接收断言的旁路信号以绕过电压调节器的输出电压，第一控制电路中的至少一个旁路第一电路或第二控制电路的输出电压旁路第二电路的输出电压，使得基本上 电压源的电压由第一电路输出到主输出节点。
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公开(公告)号：US20050083081A1
公开(公告)日：2005-04-21
申请号：US10685863
申请日：2003-10-15
申请人： Hans Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter Cook , Philip Emma , Prabhakar Kudva , Stanley Schuster
发明人： Hans Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter Cook , Philip Emma , Prabhakar Kudva , Stanley Schuster
CPC分类号： H03K19/0016
摘要： Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.
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公开(公告)号：US20130311812A1
公开(公告)日：2013-11-21
申请号：US13529161
申请日：2012-06-21
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/3203 , G06F1/329 , G06F9/4893 , G06F9/50 , Y02D10/24
摘要： Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.
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公开(公告)号：US20130311811A1
公开(公告)日：2013-11-21
申请号：US13476179
申请日：2012-05-21
申请人： Pradip Bose , Alper Buyuktosunoglu , Dilma Menezes Da Silva , Hubertus Franke , Priyanka Tembey
发明人： Pradip Bose , Alper Buyuktosunoglu , Dilma Menezes Da Silva , Hubertus Franke , Priyanka Tembey
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/3203 , G06F1/329 , G06F9/4893 , G06F9/50 , Y02D10/24
摘要： Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.
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公开(公告)号：US08564262B2
公开(公告)日：2013-10-22
申请号：US12944392
申请日：2010-11-11
IPC分类号： G05G1/56
摘要： Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node.
摘要翻译： 提供电源门控或旁路电压调节器的机制。 响应于接收到被断言的电源门信号以对所述电压调节器的输出电压进行电源门控，第一控制电路电源的至少一个功率门是第一电路或第二控制电路电路的输出电压门控第二电路的输出电压，使得 基本上没有电压被第一电路输出到主输出节点。 响应于接收断言的旁路信号以绕过电压调节器的输出电压，第一控制电路中的至少一个旁路第一电路或第二控制电路的输出电压旁路第二电路的输出电压，使得基本上 电压源的电压由第一电路输出到主输出节点。
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公开(公告)号：US08271809B2
公开(公告)日：2012-09-18
申请号：US12424161
申请日：2009-04-15
CPC分类号： G06F11/348 , G06F11/3006 , G06F11/3024 , G06F11/3062 , G06F2201/88 , Y02D10/34
摘要： Illustrative embodiments estimate power consumption within a multi-core microprocessor chip. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.
摘要翻译： 说明性实施例估计多核微处理器芯片内的功率消耗。 授权用户选择要监视的一组活动。 一组活动的每个活动的值存储在一组计数器的单独计数器中，形成一组存储的值。 该值包括计数乘以活动特有的权重因子。 该组活动被分组成子集。 将对应于每个子集中的每个活动的存储值相加，形成每个子集的总值。 每个子集的总值乘以与子集对应的因子，形成每个子集的缩放值。 将每个子集的缩放值相加，形成功率使用值。 功率管理器基于功率使用值与阈值的比较来调整单元的操作参数。
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公开(公告)号：US08271765B2
公开(公告)日：2012-09-18
申请号：US12420143
申请日：2009-04-08
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3836 , G06F11/348 , G06F2201/88 , Y02D10/34
摘要： The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.
摘要翻译： 本文描述的说明性实施例提供了一种计算机实现的方法，装置和用于管理指令的系统。 加载/存储单元在端口接收第一条指令。 响应于确定第一指令具有第一拒绝条件，加载/存储单元拒绝第一指令。 然后，指令排序单元响应于加载/存储单元来激活第一位以拒绝第一指令。 当第一位被激活时，指令排序单元阻止重新发行的第一条指令。 处理器单元确定第一指令的拒绝类。 指令排序单元启动定时器。 定时器的长度取决于第一条指令的拒绝类型。 指令排序单元重置响应定时器超时的第一位。 响应于重置第一位，指令排序单元允许第一指令变得有资格重新发行。
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40.发明申请Guarded, Multi-Metric Resource Control for Safe and Efficient Microprocessor Management 失效保护，多度量资源控制安全高效的微处理器管理公开(公告)号：US20120210328A1
公开(公告)日：2012-08-16
申请号：US13024781
申请日：2011-02-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Niti Madan
发明人： Pradip Bose , Alper Buyuktosunoglu , Niti Madan
IPC分类号： G06F9/50
CPC分类号： G06F11/3058 , G06F1/3206 , G06F1/3234 , G06F9/5094 , Y02D10/22
摘要： A mechanism is provided for guarded, multi-metric resource control. Monitoring is performed for an intended action to address a negative condition from a resource manager in a plurality of resource managers in the data processing system. Responsive to receiving the intended action, a determination is made as to whether the intended action will cause an additional negative condition within the data processing system. Responsive to determining that the intended action will cause the additional negative condition within the data processing system, at least one alternative action is identified to be implemented in the data processing system that addresses the negative condition while not causing any additional negative condition. The at least one alternative action is then implemented in the data processing system.
摘要翻译： 提供了一种用于保护的多度量资源控制的机制。 执行针对数据处理系统中的多个资源管理器中的资源管理器处理负面条件的预期动作的监视。 响应于接收预期的动作，确定预期动作是否将在数据处理系统内引起额外的负面情况。 响应于确定预期动作将导致数据处理系统内的附加负面条件，至少一个备选动作被识别为在不引起任何附加负面条件的情况下处理负条件的数据处理系统中实现。 然后在数据处理系统中实现至少一个备选动作。
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