公开(公告)号：US20150331820A1

公开(公告)日：2015-11-19

申请号：US14278682

申请日：2014-05-15

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/38

CPC classification number: G06F13/385 ,  H04L5/20 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/028

Abstract: System, methods and apparatus are described that provide an N-factorial (N!) voltage-mode driver. A method communicating on an N! interface includes encoding data in a symbol to be transmitted over the N wires of the interface, and for each wire of the N wires, calculating a resultant current for the wire by summing current flows defined for two or more two-wire combinations that include the wire, and coupling a switchable voltage source to the each wire. Each bit in the symbol defines a current flow between a pair of the N wires that is one of a plurality of possible two-wire combinations of the N wires. The switchable voltage source may be selected from a plurality of switchable voltage sources in order to provide a current in the each wire that is proportionate to the resultant current

Abstract translation: 描述了提供N阶乘法（N！）电压模式驱动器的系统，方法和装置。 一种在N！ 接口包括编码要在接口的N线上发送的符号中的数据，并且对于N线的每个线，通过将针对两个或更多个二线组合定义的电流相加来计算线的合成电流， 将可切换电压源耦合到每根导线上。 符号中的每个位定义了作为N线的多个可能的两线组合之一的一对N线之间的电流。 可切换电压源可以从多个可切换电压源中选择，以便在每根导线中提供与所得到的电流成比例的电流

公开(公告)号：US20150234774A1

公开(公告)日：2015-08-20

申请号：US14626847

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/4295

Abstract: A device is provided comprising a bus, a first set of devices, and a second set of devices. The first set of devices is coupled to the bus and configured to communicate over the bus according to a first communication protocol. The second set of devices is coupled to the bus and configured to communicate over the bus according to both the first communication protocol and a second communication protocol. In a first mode of operation, the first set of devices and second set of devices may concurrently communicate over the bus using the first communication protocol. In a second mode of operation, the second set of devices communicate with each other using the second communication protocol over the bus, and the first set of devices to stop operating on the bus.

Abstract translation: 提供了一种包括总线，第一组设备和第二组设备的设备。 第一组设备被耦合到总线并且被配置为根据第一通信协议通过总线进行通信。 第二组设备耦合到总线并且被配置为根据第一通信协议和第二通信协议通过总线进行通信。 在第一操作模式中，第一组设备和第二组设备可以使用第一通信协议通过总线同时进行通信。 在第二操作模式中，第二组设备通过总线使用第二通信协议相互通信，并且第一组设备在总线上停止工作。

公开(公告)号：US20150195211A1

公开(公告)日：2015-07-09

申请号：US14577897

申请日：2014-12-19

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L12/801

CPC classification number: H04L47/34 ,  H04L7/033 ,  H04L25/4906 ,  H04L25/493

Abstract: Systems, methods and apparatus are described for use in a communications link having a number of connectors. A method for communication using differential signaling with symbol transition clocking signaling communicates symbols over a communications link without transmitting a clock signal in a dedicated lane of the communications link. At a receiver, clock information may be extracted without using a phase-locked loop. The method includes converting data bits into a plurality of transition numbers, converting the plurality of transition numbers into a sequence of symbols, and transmitting the sequence of symbols over a plurality of signal wires. A clock signal may be embedded in transitions between consecutive symbols in the sequence of symbols. Each consecutive pair of transition numbers in the plurality of transition numbers may include two transition numbers that are different from one another. The sequence of symbols may be transmitted as a plurality of differential signals.

Abstract translation: 描述了用于具有多个连接器的通信链路中的系统，方法和装置。 一种使用具有符号转换时钟信令的差分信令的通信方法通过通信链路传送符号，而不在通信链路的专用通道中传送时钟信号。 在接收机处，可以提取时钟信息而不使用锁相环。 该方法包括将数据比特转换成多个转换号码，将多个转换号码转换为符号序列，以及通过多条信号线发送符号序列。 时钟信号可以嵌入在符号序列中的连续符号之间的转换中。 多个转移号码中的每个连续的一对转移号码可以包括彼此不同的两个转换号码。 符号序列可以作为多个差分信号发送。

公开(公告)号：US09071220B2

公开(公告)日：2015-06-30

申请号：US13832990

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H03K17/16 ,  H03H2/00 ,  H04B1/04 ,  H04L25/02 ,  H04L25/14

CPC classification number: H03H2/005 ,  H04B1/04 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/14 ,  Y02D30/30

Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

Abstract translation: 用于差分信号发射机的终端网络电路包括多个n个电阻元件和多个差分信号驱动器。 每个电阻元件的第一端在公共节点处耦合，其中n是整数值，并且是用于发送多个差分信号的导体的数量。 每个差分信号驱动器可以包括正极端子驱动器和负极端子驱动器。 正端子驱动器耦合到第一电阻元件的第二端，而负端子驱动器耦合到第二电阻元件的第二端。 正极端子驱动器和负极端子驱动器分别独立地切换以提供具有幅度和方向的电流。 在传输周期期间，每个电阻元件具有与其它电阻元件不同的幅度和/或方向的电流。

公开(公告)号：US20150120975A1

公开(公告)日：2015-04-30

申请号：US14520180

申请日：2014-10-21

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/362 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/40 ,  G06F13/4282

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. An address list may associate each of a plurality of slave devices coupled to a control data bus with a plurality of slave device identifiers. Access to the control data bus may be controlled based on the address list such that, in a first mode of operation information may be broadcast to multiple slave devices using a first group slave device identifier and, in a second mode of operation, information may be exchanged with a single slave device using an individualized slave device identifier.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 地址列表可以将耦合到控制数据总线的多个从设备中的每一个与多个从设备标识符相关联。 可以基于地址列表来控制对控制数据总线的访问，使得在第一操作模式中，信息可以使用第一组从设备标识符广播到多个从设备，并且在第二操作模式中，信息可以是 使用个性化的从设备标识符与单个从设备进行交换。

公开(公告)号：US20150100714A1

公开(公告)日：2015-04-09

申请号：US14511165

申请日：2014-10-09

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/362 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/40 ,  G06F13/4291

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two or more devices within an electronic apparatus. Embodiments disclosed herein relate to scanning for slave identifiers (SIDs) on a CCIe bus. A disclosed method includes transmitting a first inquiry on a control data bus, where the first inquiry includes a first configuration of bits, determining presence of a slave device that has a slave identifier that includes a second configuration of bits that matches the first configuration of bits, and repetitively transmitting additional inquiries on the control data bus with different configurations of bits until all bits of the slave identifier are determined The slave device may assert a response to each inquiry that includes a configuration of bits that matches a corresponding configuration of bits in the slave identifier.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个或多个设备之间。 本文公开的实施例涉及在CCIe总线上扫描从属标识符（SID）。 所公开的方法包括发送关于控制数据总线的第一询问，其中第一查询包括位的第一配置，确定具有从标识符的从设备的存在，该从属设备包括与位的第一配置匹配的位的第二配置 并且重复地发送关于具有不同配置的比特的控制数据总线的附加询问，直到从标识符的所有比特被确定。从设备可以对每个查询断言响应，该响应包括与在 从属标识符。

公开(公告)号：US20150100711A1

公开(公告)日：2015-04-09

申请号：US14485627

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/40 ,  G06F13/36

CPC classification number: G06F13/4068 ,  G06F1/04 ,  G06F13/36 ,  G06F13/4295 ,  H04L12/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: System, methods and apparatus are described for extracting data and clocks from a camera control interface bus. A transmit clock may be generated while transmitting symbols on the bus, and a receive clock may be extracted when receiving symbols from the bus. A heartbeat clock may be extracted by from symbols transmitted on the bus when the apparatus is not transmitting or receiving symbols. The transmit clock may be used to encode data in a sequence of symbols for transmission on a pair of connectors of the bus. The receive clock may be extracted by detecting transitions occurring between symbols transmitted on the bus, and generating the receive clock based on the transitions. The heartbeat clock may be used to control operations of the apparatus, or synchronize one or more function of the apparatus. The heartbeat clock may be encoded in a control word transmitted on the bus.

Abstract translation: 描述了从相机控制接口总线提取数据和时钟的系统，方法和装置。 可以在总线上发送符号时产生发送时钟，并且当从总线接收符号时可以提取接收时钟。 当设备不发送或接收符号时，可以通过在总线上发送的符号来提取心跳时钟。 发送时钟可用于以符号序列对数据进行编码，以在总线的一对连接器上进行传输。 可以通过检测在总线上发送的符号之间发生的转换以及基于转换来生成接收时钟来提取接收时钟。 心跳时钟可用于控制装置的操作，或同步装置的一个或多个功能。 心跳时钟可以在总线上发送的控制字中进行编码。

公开(公告)号：US20140372642A1

公开(公告)日：2014-12-18

申请号：US14302359

申请日：2014-06-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

公开(公告)号：US10139875B2

公开(公告)日：2018-11-27

申请号：US15067111

申请日：2016-03-10

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F1/24 ,  G06F13/40 ,  G06F13/42

Abstract: A first set of devices is coupled to a first bus, a second bus, and configured to communicate over the first bus according to a first communication protocol. A second set of devices is also coupled to the first bus and configured to communicate over the first bus according to both the first communication protocol and a second communication protocol. In a first mode, the first set of devices and second set of devices may concurrently communicate over the first bus using the first communication protocol. In a second mode, the second set of devices communicate using the second communication protocol over the bus, and the first set of devices to stop operating on the first bus. An enable command is sent by at least one of the second set of devices over a second bus to cause the first set of devices to resume activity over the first bus.

公开(公告)号：US09996488B2

公开(公告)日：2018-06-12

申请号：US15246098

申请日：2016-08-24

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/00 ,  G06F13/364 ,  G06F13/16 ,  G06F13/42 ,  G06F13/24 ,  G06F13/378 ,  G06F13/362

CPC classification number: G06F13/364 ,  G06F13/1673 ,  G06F13/24 ,  G06F13/362 ,  G06F13/378 ,  G06F13/4282

Abstract: A method for enabling 8-bit data word access over a protocol limited to 16-bit data word access is provided. Data may be encapsulated within the lowest 19 bits of a 20-bit number. If it is ascertained that an 8-bit data word is to be used in a system supporting only 16-bit data word access, a byte-enable indicator may be provided within a most significant bit of the 20-bit number while also allocating an 8-bit data region for transfer of the 8-bit data word. The 20-bit number may then be transcoded into a 12-digit ternary number, wherein a residual numerical region is defined as a number space by which a first numerical region defined for the 12-digit ternary number exceeds a second numerical region defined by the lowest 19 bits of the 20-bit number.