公开(公告)号：US20170316838A1

公开(公告)日：2017-11-02

申请号：US15645355

申请日：2017-07-10

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C29/52 ,  G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  G11C11/00

CPC classification number: G11C29/52 ,  G11C11/00 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

公开(公告)号：US20170287550A1

公开(公告)日：2017-10-05

申请号：US15085187

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Hoan Huu Nguyen ,  Keith Alan Bowman

IPC: G11C11/419 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

Abstract: Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell is disclosed. In one aspect, a leakage-aware activation control circuit is provided for a dynamic read circuit configured to perform read operations on a memory bit cell. To prevent or mitigate contention between the delayed keeper circuit and a read port circuit in the dynamic read circuit pulling a dynamic node to opposite voltage levels when a read operation is initiated, the leakage-aware activation control circuit is configured to adaptively control activation timing of the delayed keeper circuit based on a comparison of N-type Field-Effect Transistor (NFET) leakage current to P-type FET (PFET) leakage current. In this manner, the leakage-aware activation control circuit can adaptively adjust the activation timing of the delayed keeper circuit based on the actual relative strengths of NFETs and PFETs.

公开(公告)号：US09413344B2

公开(公告)日：2016-08-09

申请号：US14668041

申请日：2015-03-25

Applicant: QUALCOMM Incorporated

Inventor： Keith Alan Bowman ,  Jeffrey Todd Bridges ,  Sarthak Raina ,  Yeshwant Nagaraj Kolla ,  Jihoon Jeong ,  Francois Ibrahim Atallah ,  William Robert Flederbach ,  Jeffrey Herbert Fischer

IPC: H03H11/26 ,  H03K5/13 ,  G06F1/10 ,  H03K5/156 ,  H03K5/134 ,  H03K5/00

CPC classification number: H03K5/13 ,  G06F1/10 ,  H03K5/134 ,  H03K5/156 ,  H03K2005/00019

Abstract: Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.

Abstract translation: 公开了用于自适应时钟分配系统中关键路径时间延迟的操作校准的自动校准电路以及相关方法和系统。 自适应时钟分配系统包括可延长延迟电路，用于延迟提供给时钟电路的时钟信号的分布，以防止在向时钟控制电路供电的电源中发生电压下降之后时钟电路的时序裕度下降。 自适应时钟分配系统还包括动态变化监视器，以响应于电源中的电压下降来减小提供给时钟电路的延迟时钟信号的频率，使得时钟控制的电路在电压期间不超过其性能限制 下垂 在自适应时钟分配系统中提供自动校准电路，以在操作期间基于时钟电路的操作条件和环境条件校准动态变化监视器。

公开(公告)号：US09330785B1

公开(公告)日：2016-05-03

申请号：US14698844

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Venkatasubramanian Narayanan ,  Keith Alan Bowman ,  Alex Dongkyu Park ,  Francois Ibrahim Atallah

IPC: G11C11/00 ,  G11C29/12 ,  G11C11/419

CPC classification number: G11C11/417 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50

Abstract: In a static random access memory (SRAM), such as an SRAM cache in a processor or system-on-a-chip (SoC) device, an aging sensor is provided for testing degradation of SRAM cells comprising p-channel metal oxide semiconductor (PMOS) transistors. The minimum power supply voltage VDDMIN for the SRAM may be dynamically scaled up as the SRAM ages by performing read tests with and without the wordline overdrive voltage VWLOD.

Abstract translation: 在诸如处理器或片上系统（SoC）装置中的SRAM缓存的静态随机存取存储器（SRAM）中，提供了老化传感器，用于测试包含p沟道金属氧化物半导体的SRAM单元的劣化 PMOS）晶体管。 SRAM的最小电源电压VDDMIN可以通过执行具有和不具有字线过驱动电压VWLOD的读取测试随SRAM而老化。