公开(公告)号：US08982598B2

公开(公告)日：2015-03-17

申请号：US13865110

申请日：2013-04-17

Applicant: Rambus Inc.

Inventor： Paul Damian Franzon ,  Evan Lawrence Erickson ,  Thomas Vogelsang ,  Frederick A. Ware

IPC: G11C5/02 ,  G11C29/04 ,  G11C29/00

CPC classification number: G11C29/04 ,  G11C29/702 ,  G11C29/808

Abstract: A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide redundant circuitry to correct defective circuitry on at least one memory circuit formed on at least one layer in the stack. The redundant resources circuit includes a partial bank of redundant memory cells, wherein an aggregation of the partial bank of redundant memory cells in each of the circuit layers of the stack includes at least one full bank of redundant memory cells and wherein the redundant resources circuit is configured to replace at least one defective bank of memory cells formed on any of the circuit layers in the stack with at least a portion of the partial bank of redundant memory cells formed on any of the circuit layers in the stack.

Abstract translation: 存储器件包括电路层堆叠，每个电路层上形成有存储器电路，其被配置为存储数据，冗余资源电路被配置为提供冗余电路以校正在至少一个层上形成的至少一个存储器电路上的有缺陷的电路 堆栈。 所述冗余资源电路包括冗余存储器单元的部分组，其中所述堆叠的每个电路层中的冗余存储器单元的部分组的聚集包括至少一个全部冗余存储器单元，并且其中所述冗余资源电路为 被配置为替换形成在堆叠中的任何电路层上的至少一个存储单元的至少一个有缺陷的存储单元组，其中所述冗余存储器单元的部分库的至少一部分形成在堆叠中的任何电路层上。

公开(公告)号：US20140293102A1

公开(公告)日：2014-10-02

申请号：US14355799

申请日：2012-11-08

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  David Geoffrey Stork ,  John Eric Lindstadt ,  James E. Harris

IPC: H04N5/235

CPC classification number: H04N5/235 ,  H04N1/00769 ,  H04N5/2355 ,  H04N5/3355 ,  H04N5/3535 ,  H04N5/355 ,  H04N5/35536 ,  H04N5/3745

Abstract: Pixel circuits in an image sensor are sampled repetitively during an image frame period. At each sampling, a signal indicative of the photocharge integrated by a pixel circuit since last reset is compared to a threshold. If the integrated photocharge signal has not reached the threshold, the pixel circuit is permitted to continue integrating photocharge. If the integrated photocharge signal has reached the threshold, the pixel circuit is reset to remove integrated photocharge and photocharge integration for that pixel circuit is restarted. A corresponding pixel circuit value is recorded for the reset pixel circuit.

Abstract translation: 图像传感器中的像素电路在图像帧周期期间重复采样。 在每次采样时，将与上一次复位后的像素电路集成的光电荷的信号与阈值进行比较。 如果集成光电荷信号尚未达到阈值，则允许像素电路继续积分光电荷。 如果积分的光电荷信号已经达到阈值，则像素电路被复位以去除集成的光电荷并且该像素电路的光电荷积分被重新启动。 记录复位像素电路的对应像素电路值。

公开(公告)号：US20140289574A1

公开(公告)日：2014-09-25

申请号：US14353401

申请日：2012-10-19

Applicant: RAMBUS INC.

Inventor： Ely Tsern ,  Frederick A. Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24

CPC classification number: G06F11/1008 ,  G11C5/04 ,  G11C29/24 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Abstract translation: 公开了一种在集成电路（IC）存储器件中的操作方法。 该方法包括以第一刷新率刷新IC存储设备中的第一组存储行。 测试每行的保留时间。 对被测试给定行的测试包括以比第一刷新率慢的第二刷新率刷新。 测试可以基于存储在给定行中的数据的访问请求而中断。

公开(公告)号：US20250021484A1

公开(公告)日：2025-01-16

申请号：US18782890

申请日：2024-07-24

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Frederick A. Ware ,  Michael Raymond Miller ,  Collins Williams

IPC: G06F12/0864

Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.

公开(公告)号：US12190990B2

公开(公告)日：2025-01-07

申请号：US18373162

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C5/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US12190974B2

公开(公告)日：2025-01-07

申请号：US18138661

申请日：2023-04-24

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24 ,  G06F11/10 ,  G11C29/50 ,  G11C5/04 ,  G11C29/44

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US20240428840A1

公开(公告)日：2024-12-26

申请号：US18750027

申请日：2024-06-21

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Thomas Vogelsang

IPC: G11C11/406

Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple regions. Monitoring circuitry is coupled to each of the multiple regions to detect and generate per-region operating parameter information. Refresh circuitry generates per-region refresh information for the multiple regions based on the per-region operating parameter information.

公开(公告)号：US12170126B2

公开(公告)日：2024-12-17

申请号：US18420688

申请日：2024-01-23

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/48 ,  H01L25/065 ,  H10B12/00

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US20240404575A1

公开(公告)日：2024-12-05

申请号：US18740400

申请日：2024-06-11

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C11/406

Abstract: An integrated circuit memory device is disclosed. The memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh parameters. Refresh logic refreshes each segment in accordance with the corresponding per-segment value.

公开(公告)号：US20240371432A1

公开(公告)日：2024-11-07

申请号：US18643674

申请日：2024-04-23

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C11/4091 ,  G11C7/06 ,  G11C7/08

Abstract: A sense amplifier for a memory device includes a primary latch and a holding latch that are independently controllable. The primary latch comprises a first set of transistors and the holding latch includes a second set of transistors having higher threshold voltages than the first set of transistors. In conjunction with a memory access operation, the primary latch and the holding latch sense and amplify a differential voltage of a pair of bitlines. A connectivity control circuit controls connectivity of the primary latch in different operational modes including pre-charge, offset pre-compensation, and amplification. In an active idle mode in between memory access operations while the wordline may remain active, the connectivity control circuit may turn off the primary latch while the holding latch holds the differential voltage on the bitlines to avoid leakage current through the primary latch.