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    DATA TRANSMISSION USING DELAYED TIMING SIGNALS
    1.
    发明申请
    DATA TRANSMISSION USING DELAYED TIMING SIGNALS 有权

    公开(公告)号：US20240372542A1

    公开(公告)日：2024-11-07

    申请号：US18638218

    申请日：2024-04-17

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G06F13/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Data transmission using delayed timing signals
    3.
    发明授权
    Data transmission using delayed timing signals 有权

    公开(公告)号：US11451218B2

    公开(公告)日：2022-09-20

    申请号：US16880694

    申请日：2020-05-21

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G06F13/16 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22 ,  G06F13/42 ,  G06F13/00 ,  G11C7/04

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Memory system topologies including a memory die stack
    4.
    发明授权
    Memory system topologies including a memory die stack 有权

    公开(公告)号：US11328764B2

    公开(公告)日：2022-05-10

    申请号：US17323889

    申请日：2021-05-18

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

    IPC: G11C7/00 ,  G11C11/4093 ,  H01L25/065 ,  H01L25/10 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L25/18 ,  H01L23/00

    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

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