公开(公告)号：US20170177021A1

公开(公告)日：2017-06-22

申请号：US15391299

申请日：2016-12-27

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/08 ,  G06F13/16

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F13/1673 ,  G06F13/1689 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/10 ,  Y02D10/14

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US09564885B2

公开(公告)日：2017-02-07

申请号：US14361575

申请日：2012-11-16

Applicant: Rambus Inc.

Inventor： Pak Shing Chau ,  Wayne S. Richardson ,  Jun Kim

IPC: H03K3/017 ,  H03K5/156 ,  H03K3/012

CPC classification number: H03K5/1565 ,  H03K3/012 ,  H03K3/017

Abstract: Duty cycle error vectors that indicate both the magnitude and direction of the duty cycle error relative to a desired duty cycle are generated within a duty cycle measurement circuit, enabling threshold-based determination of whether duty cycle adjustment is necessary, refraining from power-consuming adjustment and follow-up measurement in those cases where the duty cycle is within a target range. When duty cycle adjustment is deemed necessary, the magnitude of the duty cycle error indicated by the duty cycle error vector may be applied to effect proportional rather than incremental duty cycle adjustment, quickly returning the clock duty cycle to a target range.

Abstract translation: 在占空比测量电路内产生指示相对于期望占空比的占空比误差的大小和方向的占空比误差矢量，使得能够基于阈值确定是否需要占空比调整，避免功耗调节 在占空比在目标范围内的情况下进行跟踪测量。 当认为有必要进行占空比调整时，由占空比误差矢量表示的占空比误差的大小可以用于实现比例而不是增量占空比调整，从而快速地将时钟占空比返回到目标范围。

公开(公告)号：US09235537B2

公开(公告)日：2016-01-12

申请号：US13656498

申请日：2012-10-19

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/00 ,  G06F13/16 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F13/1673 ,  G06F13/1689 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/10 ,  Y02D10/14

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

Abstract translation: 一种存储器系统，其中通过测量在具有低于第一定时的频率的第二定时信号中出现的实际相位延迟来确定在存储器件中用于数据传输的第一定时信号的分配中将发生的定时漂移 并且分布在模拟第一定时信号的分布的至少一部分的漂移特性的一个或多个电路中。 实际的相位延迟在存储器件中确定并提供给存储器控制器，使得用于数据传输的定时信号的相位可以基于所确定的定时漂移来调整。

公开(公告)号：US20240282354A1

公开(公告)日：2024-08-22

申请号：US18590221

申请日：2024-02-28

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/02

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US11948619B2

公开(公告)日：2024-04-02

申请号：US18181185

申请日：2023-03-09

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C7/00 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/02

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US11797227B2

公开(公告)日：2023-10-24

申请号：US16405479

申请日：2019-05-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4097 ,  G11C8/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

公开(公告)号：US20220254407A1

公开(公告)日：2022-08-11

申请号：US17568656

申请日：2022-01-04

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US20210174865A1

公开(公告)日：2021-06-10

申请号：US17103374

申请日：2020-11-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C11/4074 ,  G11C7/20 ,  G11C7/02 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US10672450B2

公开(公告)日：2020-06-02

申请号：US16139636

申请日：2018-09-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C8/00 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US10439740B2

公开(公告)日：2019-10-08

申请号：US15652047

申请日：2017-07-17

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

IPC: G06F19/00 ,  H04B17/11 ,  H04L5/14 ,  H04L25/03

Abstract: A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.