公开(公告)号：US20150054045A1

公开(公告)日：2015-02-26

申请号：US14532914

申请日：2014-11-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/11575 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L27/0922 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/792

Abstract: Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.

Abstract translation: 提供了一种提高包括分离栅结构中的非易失性存储单元的半导体器件的制造成品率的技术。 形成CG分流部的选择栅电极，使得位于馈电区域的CG分流部的选择栅电极的半导体衬底的主表面的第二高度d2低于选择区域的第一高度d1 栅极电极从存储单元形成区域中的半导体衬底的主表面。

公开(公告)号：US08896053B2

公开(公告)日：2014-11-25

申请号：US13740045

申请日：2013-01-11

Applicant: Renesas Electronics Corporation

Inventor： Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L29/792 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/788 ,  H01L27/092 ,  H01L21/28 ,  H01L49/02 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/115

CPC classification number: H01L27/11575 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L27/0922 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/792

Abstract: Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.

Abstract translation: 提供了一种提高包括分离栅结构中的非易失性存储单元的半导体器件的制造成品率的技术。 形成CG分流部的选择栅电极，使得位于馈电区域的CG分流部的选择栅电极的半导体衬底的主表面的第二高度d2低于选择区域的第一高度d1 栅极电极从存储单元形成区域中的半导体衬底的主表面。

公开(公告)号：US08853036B2

公开(公告)日：2014-10-07

申请号：US14138036

申请日：2013-12-21

Applicant: Renesas Electronics Corporation

Inventor： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L29/66 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

公开(公告)号：US08507340B2

公开(公告)日：2013-08-13

申请号：US13772470

申请日：2013-02-21

Applicant: Renesas Electronics Corporation

Inventor： Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract translation: 在半导体衬底上形成具有控制栅电极，其上的第一绝缘膜和其上的第二绝缘膜的叠层图案。 与层压图案相邻地形成存储栅电极。 在控制栅极和半导体衬底之间形成栅极绝缘膜。 在存储栅电极和半导体衬底之间以及叠层图案和存储栅电极之间形成第四绝缘膜，其包括氧化硅膜的叠层膜，氮化硅膜和另一氧化硅膜。 在与存储栅电极相邻的层叠图案侧的侧壁处，第一绝缘膜从控制栅极电极和第二绝缘膜退回，并且控制栅电极的上端角部分被倒圆。

公开(公告)号：US09520504B2

公开(公告)日：2016-12-13

申请号：US14190183

申请日：2014-02-26

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima

IPC: H01L29/792 ,  H01L29/66 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

Abstract: In an MONOS-type memory cell with a split gate structure, short circuit between a selection gate electrode and a memory gate electrode is prevented, and reliability of a semiconductor device is improved. In a MONOS memory having a selection gate electrode and a memory gate electrode that are adjacent to each other and that extend in a first direction, an upper surface of the selection gate electrode in a region except for a shunt portion at an end portion of the selection gate electrode in the first direction is covered with a cap insulating film. The memory gate electrode is terminated on the cap insulating film side with respect to a border between the cap insulating film and an upper surface of the shunt portion exposed from the cap insulating film.

Abstract translation: 在具有分离栅极结构的MONOS型存储单元中，防止了选择栅电极和存储栅电极之间的短路，提高了半导体器件的可靠性。 在具有彼此相邻并且沿第一方向延伸的选择栅电极和存储栅电极的MONOS存储器中，在除了在第一方向的端部处的分流部分之外的区域中的选择栅电极的上表面 第一方向的选择栅极电极被帽绝缘膜覆盖。 存储栅电极相对于帽绝缘膜与从帽绝缘膜露出的分流部的上表面之间的边界在帽绝缘膜侧终止。

公开(公告)号：US09443991B2

公开(公告)日：2016-09-13

申请号：US15062160

申请日：2016-03-06

Applicant: Renesas Electronics Corporation

Inventor： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/06 ,  H01L23/535 ,  H01L23/532 ,  H01L27/115

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

Abstract translation: 在存储单元（MC）的馈电区域中，在存储单元（MC）的馈电区域中，通过自对准在存储器nMIS（Qnm）的选择栅极（CG）的侧表面上提供存储器nMIS（Qnm）的侧壁形状的存储栅极（MG） 通过绝缘膜选择nMIS（Qnc），向存储栅电极（MG）提供电压的插头（PM）嵌入在形成在存储栅上的层间绝缘膜（9）中形成的接触孔（CM） 电极（MG）并且电连接到存储栅电极（MG）。 由于在选择栅电极（CG）的上表面上形成帽绝缘膜（CAP），所以可以防止插头（PM）与选择栅电极（CG）之间的导电。

公开(公告)号：US20160204116A1

公开(公告)日：2016-07-14

申请号：US15073524

申请日：2016-03-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

公开(公告)号：US20160035734A1

公开(公告)日：2016-02-04

申请号：US14802050

申请日：2015-07-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

Abstract translation: 提高了半导体器件的性能。 在制造半导体器件的方法中，在存储单元区域中，在半导体衬底的主表面上形成由第一导电膜形成的控制栅电极。 然后，以覆盖控制栅电极的方式形成绝缘膜和第二导电膜，并且将第二导电膜回蚀刻。 结果，第二导电膜经由绝缘膜留在控制栅电极的侧壁上，从而形成存储栅电极。 然后，在外围电路区域中，在半导体衬底的主表面上形成p型阱。 在p型阱上形成第三导电膜。 然后，形成由第三导电膜形成的栅电极。

公开(公告)号：US20150325583A1

公开(公告)日：2015-11-12

申请号：US14803060

申请日：2015-07-18

Applicant: Renesas Electronics Corporation

Inventor： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L27/115

CPC classification number: H01L27/11563 ,  G11C16/0466 ,  H01L27/1052 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66477 ,  H01L29/66833 ,  H01L29/792

Abstract: A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.

Abstract translation: 在相同的半导体衬底上形成非易失性存储器和电容元件的存储单元。 存储单元包括经由第一绝缘膜形成在半导体衬底上的控制栅极电极，经由第二绝缘膜在半导体衬底上与控制栅电极相邻形成的存储栅电极，并且其中具有电荷存储的第二绝缘膜 一部分。 电容元件包括由与控制栅电极相同的硅膜层形成的下电极，由与第二绝缘膜相同的绝缘膜形成的电容绝缘膜和由相同的硅层形成的上电极 薄膜作为记忆栅电极。 上部电极的杂质浓度高于记忆栅电极的浓度。

公开(公告)号：US20150287736A1

公开(公告)日：2015-10-08

申请号：US14745340

申请日：2015-06-19

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film,. and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

Abstract translation: 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜形成。 以及位于第一硅区上方的第二硅区。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。