公开(公告)号：US20150287746A1

公开(公告)日：2015-10-08

申请号：US14674838

申请日：2015-03-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroki SHINKAWATA ,  Toshiaki IWAMATSU

IPC: H01L27/12 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L21/027 ,  H01L29/167 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/76229 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0207 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78621

Abstract: In a step F2, an isolation region and an element formation region are formed in an SOI substrate. In a step F3, an SOI region and a bulk region are formed. Here, an isolation insulating film of the isolation region is exposed along the entire perimeter of a sidewall of a step between the SOI region and the bulk region. In a step F4, a gate electrode is formed. In a step F5, extension implantation of a bulk transistor is carried out. Here, treatment for preventing an impurity for extension implantation from being implanted into the SOI region is performed. In a step F6, an elevated epitaxial layer is formed in the SOI region.

Abstract translation: 在步骤F2中，在SOI衬底中形成隔离区域和元件形成区域。 在步骤F3中，形成SOI区域和体区域。 这里，隔离区域的隔离绝缘膜沿着SOI区域和主体区域之间的台阶侧壁的整个周边露出。 在步骤F4中，形成栅电极。 在步骤F5中，进行体晶体管的延伸注入。 这里，进行用于防止用于延伸注入的杂质的注入到SOI区域的处理。 在步骤F6中，在SOI区域中形成升高的外延层。

公开(公告)号：US20150221560A1

公开(公告)日：2015-08-06

申请号：US14686828

申请日：2015-04-15

Applicant: Renesas Electronics Corporation

Inventor： Katsuyuki HORITA ,  Toshiaki IWAMATSU ,  Hideki MAKIYAMA ,  Yoshiki YAMAMOTO

IPC: H01L21/84 ,  H01L21/768 ,  H01L21/28 ,  H01L21/283 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/84 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/486 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

Abstract translation: 提高了半导体器件的特性。 本发明的半导体器件包括：（a）布置在由元件隔离区包围的半导体区域形成的有源区中的MISFET; 和（b）布置在有源区下方的绝缘层。 此外，半导体器件包括：（c）布置在有源区下方以插入绝缘层的p型半导体区域; 和（d）布置在p型半导体区域下方的导电类型与p型相反的n型半导体区域。 并且，p型半导体区域包括从绝缘层的下方延伸的连接区域，并且MIS型的p型半导体区域和栅极电极通过作为一体形成的导电膜的共享插头彼此连接 从栅电极上方延伸到连接区域的上方。

公开(公告)号：US20130187230A1

公开(公告)日：2013-07-25

申请号：US13747537

申请日：2013-01-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract translation: 防止在SOI衬底上发生MOSFET的短沟道特性和寄生电容。 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。