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公开(公告)号：US06175930B1
公开(公告)日：2001-01-16
申请号：US09024586
申请日：1998-02-17
IPC分类号： H02H305
CPC分类号： G06F12/0831
摘要： A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation—one which might affect the storage hierarchy as perceived by other devices within the system—is posted in the snoop queue of a remote snooping device. The flag remains set and is reset only when a synchronization instruction (such as the “sync” instruction supported by the PowerPC™ family of devices) is received from a local processor. The state of the flag thus provides historical information regarding architected operations which may be pending in other devices within the system after being snooped from the system bus. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered and additional system bus cycles made available for other purposes. When a local processor issues a synchronization instruction to the device managing the architected logic queue, the instruction is generally accepted when the architected logic queue is empty. Otherwise the architected operation is retried back to the local processor until the architected logic queue becomes empty. If the flag is set when the synchronization instruction is accepted from the local processor, it is presented on the system bus. If the flag is not set when the synchronization instruction is received from the local processor, the synchronization operation is unnecessary and is not presented on the system bus.
摘要翻译： 与多处理器系统中的存储器相干设备的架构化逻辑队列相关联的寄存器包含标志集，每当可以影响系统内其他设备感知到的存储层次结构的操作（一个可能影响系统中的其他设备的架构操作）被发布在 一个远程监听设备。 该标志保持置位，并且仅当从本地处理器接收到同步指令（例如由PowerPC TM系列器件支持的“sync”指令）时才会复位该标志。 因此，标志的状态提供关于在从系统总线窥探之后可能在系统内的其他设备中挂起的架构操作的历史信息。 该历史信息用于确定是否应在系统总线上呈现同步操作，从而允许滤除不必要的同步操作，并为其他目的提供额外的系统总线周期。 当本地处理器向管理架构的逻辑队列的设备发出同步指令时，当架构的逻辑队列为空时，通常会接受该指令。 否则，架构操作将重新回到本地处理器，直到架构化的逻辑队列变为空。 如果在本地处理器接受同步指令时设置了标志，则会将其显示在系统总线上。 如果当从本地处理器接收到同步指令时未设置标志，则不需要同步操作，并且不会在系统总线上呈现同步操作。
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32.发明授权Method and apparatus for monitoring 60x bus signals at a reduced frequency 失效用于以降低的频率监视60x总线信号的方法和装置
公开(公告)号：US6092132A
公开(公告)日：2000-07-18
申请号：US175612
申请日：1998-10-19
CPC分类号： G06F13/4213
摘要： An apparatus and method for monitoring a PowerPC 60x bus within an integrated circuit is described. The 60x bus operates at a particular frequency, f.sub.b. An image of the 60x bus is produced, operating at a lower frequency of operations, f.sub.o, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Masking circuitry within the driver/receiver circuitry masks bi-directional signals, such as ARTRY.sub.-- and SHD.sub.--, during the pre-charge cycles, when these bi-directional signals are in an unpredictable state. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be "out-of-phase" with respect to one another. A buffer/align unit is used to bring each of the monitored signals back in phase relative to one another. Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, f.sub.o. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, f.sub.o.
摘要翻译： 描述了用于监视集成电路内的PowerPC 60x总线的装置和方法。 60x总线以特定频率fb运行。 生产60x总线的图像，操作频率较低，更适合于测试设备的监控。 使用驱动器/接收器电路从信号接收和驱动到总线。 信号可以是仅输入信号，仅输出信号或双向信号。 要监视的信号被点击在驱动器/接收器电路中。 当这些双向信号处于不可预测状态时，驱动器/接收器电路内的屏蔽电路在预充电周期期间屏蔽双向信号，例如ARTRY-和SHD-。 根据驱动器/接收器逻辑中的信号抽头的布置，信号可能相对于彼此“异相”。 使用缓冲器/对准单元使每个被监视的信号相对于彼此同相。 编码电路以以更低的操作频率fo产生总线的图像的方式对总线的时间延迟版本进行编码。 编码电路在编码窗口中考虑监视信号的值，并且以较低的操作频率fo产生每个信号的编码值。
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33.发明授权Apparatus and method for separately layering cache and architectural specific functions in different operational controllers 失效用于在不同操作控制器中单独分层缓存和架构特定功能的装置和方法
公开(公告)号：US6061762A
公开(公告)日：2000-05-09
申请号：US839442
申请日：1997-04-14
CPC分类号： G06F12/0802
摘要： Cache and architectural specific functions are layered within a controller, simplifying design requirements. Faster performance may be achieved and individual segments of the overall design may be individually tested and formally verified. Transition between memory consistency models is also facilitated. Different segments of the overall design may be implemented in distinct integrated circuits, allowing less expensive processes to be employed where suitable.
摘要翻译： 缓存和架构特定功能在控制器内分层，简化了设计要求。 可以实现更快的性能，并且可以单独测试和正式验证整体设计的各个部分。 内存一致性模型之间的转换也是有利的。 总体设计的不同部分可以在不同的集成电路中实现，从而允许在合适的情况下采用较便宜的工艺。
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34.发明授权Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two pseudo-random priority weights 失效用于控制对共享资源的访问的方法和系统，其中至少一个请求者被同时分配至少两个伪随机优先权重
公开(公告)号：US5931924A
公开(公告)日：1999-08-03
申请号：US839437
申请日：1997-04-14
IPC分类号： G06F15/16 , G06F13/364 , G06F15/177 , G06F13/14
CPC分类号： G06F13/364
摘要： A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is associated with a priority weight that indicates a probability that the associated requester will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requesters. In response to the current priorities of the requesters, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.
摘要翻译： 描述了用于控制对数据处理系统中的共享资源的访问的方法和系统。 根据该方法，通过共享资源的多个请求者生成对资源的访问的多个请求。 每个请求者与优先级权重相关联，该权重指示相关请求者将被分配最高当前优先级的概率。 然后分配每个请求者相对于请求者的先前优先级基本随机确定的当前优先级。 为响应请求者的当前优先级，授予访问资源的请求。 在一个实施例中，与被许可的请求相对应的请求者用信号通知其请求已经被许可，并且与被拒绝的请求相对应的请求者用信号通知其请求未被授予。
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35.发明授权High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system 失效适用于多处理器数据处理系统锁定采集的高速推广机制公开(公告)号：US07213248B2
公开(公告)日：2007-05-01
申请号：US10268729
申请日：2002-10-10
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect. Advantageously, promotion bit fields are handled separately from data, and the communication of promotion bit fields does not entail the movement of data cache lines.
摘要翻译： 多处理器数据处理系统包括耦合到互连的多个处理器和包含至少一个促销位字段的全局推广设备。 第一处理器执行包括负载型指令的高速指令序列，以在除了至少第二处理器之外的全局促进设备中获取促销位字段。 所述请求可以被耦合到互连的所有处理器可见。 响应于负载型指令的执行，第一处理器的寄存器接收指示通过执行负载型指令是否获取了促销位字段的寄存器位字段。 虽然第一处理器保持不属于第二处理器的升级位字段，但允许第二处理器在互连上发起请求。 优选地，促销比特字段与数据分开处理，并且促销比特字段的通信不需要数据高速缓存行的移动。
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36.发明授权Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction 失效通过执行分支式指令访问全球推广工具的方法，装置和系统公开(公告)号：US06925551B2
公开(公告)日：2005-08-02
申请号：US10268742
申请日：2002-10-10
CPC分类号： G06F12/0831 , G06F9/3004 , G06F9/30054 , G06F9/30072 , G06F9/30087
摘要： A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. The first processor initiates execution of a branch-type instruction to request acquisition of a promotion bit field exclusive of at least the second processor. In response to the branch-type instruction, the first processor issues an access request to acquire the promotion bit field. After the accessing request, a register of the first processor receives a register bit indicating whether or not the promotion bit field was successfully acquired by the access request. As a part of executing the branch-type instruction, the first processor selects among a first execution path and a second execution path in response to the register bit.
摘要翻译： 多处理器数据处理系统包括耦合到互连的第一和第二处理器以及包含至少一个促销位字段的全局推广设备。 第一处理器启动分支型指令的执行，以请求获取除了至少第二处理器之外的促销位字段。 响应于分支型指令，第一处理器发出获取促销位字段的访问请求。 在访问请求之后，第一处理器的寄存器接收指示是否通过访问请求成功获取了促销位字段的寄存器位。 作为执行分支型指令的一部分，第一处理器响应于寄存器位在第一执行路径和第二执行路径之中进行选择。
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37.发明授权Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bus operations 失效用于执行多重启动的多来源可变延迟系统总线操作的方法和装置
公开(公告)号：US6128705A
公开(公告)日：2000-10-03
申请号：US4148
申请日：1998-01-07
CPC分类号： G06F12/0831
摘要： A method and apparatus for preventing the occurrence of deadlocks from the execution of multiply-initiated multiply-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.
摘要翻译： 一种用于防止从多次发起的多来源可变延迟系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者除了按照约定的条件同时给定操作。 换句话说，即使在重试操作时，给定缓存中的监听器也可以接受操作并开始处理。 此外，没有一个主动侦听器释放一个操作，直到所有的主动侦听器都完成了操作。 换句话说，给定操作的执行由窥探者同时开始，同时由每个窥探者完成。 这可以防止乒乓的死锁，因为任何一个缓存都不会在其他任何缓存之前完成操作。
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38.发明授权Apparatus and method of layering cache and architectural specific functions to permit generic interface definition 失效分层缓存和架构特定功能以允许通用接口定义的装置和方法
公开(公告)号：US6122691A
公开(公告)日：2000-09-19
申请号：US224105
申请日：1999-01-04
CPC分类号： G06F12/0897 , G06F12/0893 , G06F13/1694
摘要： Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.
摘要翻译： 高速缓存控制器中的缓存和架构功能是分层的，并具有通用接口。 分层缓存和架构操作允许在控制器内的控制器逻辑和总线接口单元之间定义通用接口。 通用接口通过将支持的操作的本质提取到通用协议中来定义。 接口本身可以是脉冲或保持的接口，这取决于操作的特性。 由于控制器逻辑与处理器或总线架构所需的特定协议隔离，所以可以通过适当地修改总线接口单元将设计直接传送到不同协议或处理器的新控制器。
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39.发明授权Method of layering cache and architectural specific functions to promote operation symmetry 失效分层缓存和架构特定功能的方法，以促进操作对称
公开(公告)号：US6061755A
公开(公告)日：2000-05-09
申请号：US839441
申请日：1997-04-14
CPC分类号： G06F12/0831
摘要： Cache and architectural functions within a cache controller are layered so that architectural operations may be symmetrically treated regardless of whether initiated by a local processor or by a horizontal processor. The same cache controller logic which handles architectural operations initiated by a horizontal device also handles architectural operations initiated by a local processor. Architectural operations initiated by a local processor are passed to the system bus and self-snooped by the controller. If necessary, the architectural controller changes the operation protocol to conform to the system bus architecture.
摘要翻译： 高速缓存控制器内的缓存和架构功能被分层，使得架构操作可以被对称地处理，而不管是由本地处理器还是由水平处理器启动。 处理由水平设备发起的架构操作的相同缓存控制器逻辑也处理由本地处理器启动的架构操作。 由本地处理器启动的架构操作被传递给系统总线，并由控制器自行侦测。 如果需要，架构控制器改变操作协议以符合系统总线体系结构。
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40.发明授权
公开(公告)号：US5951668A
公开(公告)日：1999-09-14
申请号：US934407
申请日：1997-09-19
CPC分类号： G06F13/4013 , G06F13/36
摘要： A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the ordered data on a second bus having the second ordering policy. The system includes a plurality of execution units for storing operations and executing the transfer of data between the first and second buses. Each one of the execution units are assigned to a group which represent a class of operations. The apparatus further includes intra prioritizing means, for each group, for prioritizing the stored operations according to the second ordering policy exclusive of the operation stored in the other group. The system also includes inter prioritizing means for determining which one of the prioritized operations can proceed to execute according to the second ordering policy.
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