Method of fabricating a gallium nitride merged P-i-N Schottky (MPS) diode by regrowth and etch back
    33.
    发明授权
    Method of fabricating a gallium nitride merged P-i-N Schottky (MPS) diode by regrowth and etch back 有权
    通过再生长和回蚀刻制造氮化镓合并的P-i-N肖特基(MPS)二极管的方法

    公开(公告)号:US08969994B2

    公开(公告)日:2015-03-03

    申请号:US13585121

    申请日:2012-08-14

    摘要: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.

    摘要翻译: MPS二极管包括以第一导电类型和第一掺杂剂浓度为特征的III族氮化物衬底,其具有第一侧和第二侧。 MPS二极管还包括III族氮化物外延结构,其包括耦合到衬底的第一侧的第一III族氮化物外延层,其中第一III族氮化物外延层的区域包括突起阵列。 III族氮化物外延结构还包括多个第二导电类型的III族氮化物区域,每个部分设置在相邻的突起之间。 第二导电类型的多个III族氮化物区域中的每一个包括横向位于相邻突起之间的第一部分和沿着垂直于衬底的第一侧的方向延伸的第二部分。 MPS二极管还包括电耦合到一个或多个突起和一个或多个第二部分的第一金属结构。

    Method of fabricating a GaN P-i-N diode using implantation
    37.
    发明授权
    Method of fabricating a GaN P-i-N diode using implantation 有权
    使用注入制造GaN P-i-N二极管的方法

    公开(公告)号:US08822311B2

    公开(公告)日:2014-09-02

    申请号:US13335329

    申请日:2011-12-22

    IPC分类号: H01L29/20 H01L29/24

    摘要: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.

    摘要翻译: III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区,并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于与注入区域相邻的第一III族氮化物外延材料的部分具有降低的导电性。

    GAN vertical superjunction device structures and fabrication methods
    38.
    发明授权
    GAN vertical superjunction device structures and fabrication methods 有权
    GAN垂直超结装置结构及制造方法

    公开(公告)号:US08785975B2

    公开(公告)日:2014-07-22

    申请号:US13529822

    申请日:2012-06-21

    摘要: A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

    摘要翻译: 半导体器件包括第一导电类型的III族氮化物衬底,耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构,第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分,以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。

    GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS
    39.
    发明申请
    GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS 有权
    GAN垂直超导装置结构和制造方法

    公开(公告)号:US20130341677A1

    公开(公告)日:2013-12-26

    申请号:US13529822

    申请日:2012-06-21

    IPC分类号: H01L27/088 H01L21/8234

    摘要: A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

    摘要翻译: 半导体器件包括第一导电类型的III族氮化物衬底,耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构,第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分,以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。

    Silicon nitride passivation with ammonia plasma pretreatment for improving reliability of AlGaN/GaN HEMTs
    40.
    发明授权
    Silicon nitride passivation with ammonia plasma pretreatment for improving reliability of AlGaN/GaN HEMTs 失效
    氮化硅钝化与氨等离子体预处理,以提高AlGaN / GaN HEMTs的可靠性

    公开(公告)号:US07338826B2

    公开(公告)日:2008-03-04

    申请号:US11311592

    申请日:2005-12-09

    摘要: This invention pertains to an electronic device and to a method for making it. The device is a heterojunction transistor, particularly a high electron mobility transistor, characterized by presence of a 2 DEG channel. Transistors of this invention contain an AlGaN barrier and a GaN buffer, with the channel disposed, when present, at the interface of the barrier and the buffer. Surface treated with ammonia plasma resembles untreated surface. The method pertains to treatment of the device with ammonia plasma prior to passivation to extend reliability of the device beyond a period of time on the order of 300 hours of operation, the device typically being a 2 DEG AlGaN/GaN high electron mobility transistor with essentially no gate lag and with essentially no rf power output degradation.

    摘要翻译: 本发明涉及一种电子设备及其制造方法。 该器件是异质结晶体管,特别是高电子迁移率晶体管,其特征在于存在2°通道。 本发明的晶体管包含AlGaN势垒和GaN缓冲器,其中通道设置在阻挡层和缓冲器的界面处。 用氨等离子体进行表面处理与未处理的表面相似。 该方法涉及在钝化之前用氨等离子体处理器件,以将器件的可靠性延长超过约300小时的操作时间,该器件通常为2°AlGaN / GaN高电子迁移率晶体管,其基本上 没有门滞,并且基本上没有rf功率输出降级。