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31.发明授权Method and system for managing distributed arbitration for multicycle data transfer requests 失效用于管理多周期数据传输请求的分布式仲裁的方法和系统公开(公告)号：US06950892B2
公开(公告)日：2005-09-27
申请号：US10411463
申请日：2003-04-10
IPC分类号： G06F13/372 , G06F12/00 , G06F12/08 , G06F13/14 , G06F13/364 , G06F13/368
CPC分类号： G06F13/364 , G06F12/0846
摘要： A method and system for managing distributed arbitration for multi-cycle data transfer requests provides improved performance in a processing system. A multi-cycle request indicator is provided to a slice arbiter and if a multi-cycle request is present, only one slice is granted its associated bus. The method further blocks any requests from other requesting slices having a lower latency than the first slice until the latency difference between the other requesting slices and the longest latency slice added to a predetermined cycle counter value has expired. The method also blocks further requests from the first slice until the predetermined cycle counter value has elapsed and blocks requests from slices having a higher latency than the first slice until the predetermined cycle counter value less the difference in latencies for the first slice and for the higher latency slice has elapsed.
摘要翻译： 用于管理多循环数据传输请求的分布式仲裁的方法和系统在处理系统中提供改善的性能。 多周期请求指示符被提供给切片仲裁器，并且如果存在多周期请求，则只有一个切片被授予其相关联的总线。 该方法进一步阻止来自具有比第一片低的等待时间的其他请求片的任何请求，直到其他请求片之间的等待时间差与添加到预定周期计数值的最长等待时间片已经期满为止。 该方法还阻止来自第一片的进一步请求，直到经过了预定周期计数器值，并且阻止来自具有比第一片的更高等待时间的片的请求，直到预定周期计数值减去第一片的延迟差和较高 延迟片已过。
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公开(公告)号：US06748501B2
公开(公告)日：2004-06-08
申请号：US09752948
申请日：2000-12-30
IPC分类号： G06F1200
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087 , G06F12/0846 , G06F12/0855
摘要： A method of storing values in a sliced cache by providing separate, but coordinated, reservation units for each cache slice. When a load-with-reserve (larx) operation is issued from the processor core as part of an atomic read-modify-write sequence, a message is broadcast to each of the cache slices to clear reservation flags in the slices; a reservation flag is also set in the target cache slice, and a memory address associated with the load-with-reserve operation is loaded into a reservation unit of the target cache slice. When a conditional store operation is issued from the core to complete the atomic read-modify-write sequence, a second message is broadcast to any non-target cache slice of the processing unit to clear reservation flags in the non-target cache slice(s). The conditional store operation passes if the reservation flag of the target cache slice is still set, and the memory address associated with the conditional store operation matches the memory address loaded in a reservation unit of the target cache slice. The broadcast messages coordinate the reservation units and facilitate the use of larger sliced caches.
摘要翻译： 通过为每个高速缓冲存储器片提供单独的但协调的预留单元来将值存储在切片高速缓存中的方法。 当作为原子读取 - 修改 - 写入序列的一部分从处理器核心发出装载保留（Larx）操作时，向每个缓存片段广播消息以清除片中的预留标志; 在目标高速缓冲存储器片中也设置预约标志，并且将与加载备份操作相关联的存储器地址加载到目标高速缓冲存储器片段的预留单元中。 当从核心发出条件存储操作以完成原子读 - 修改 - 写序列时，将第二消息广播到处理单元的任何非目标缓存片，以清除非目标高速缓冲存储器片段中的保留标志 ）。 如果目标高速缓冲存储器片段的预留标志仍然被设置，则条件存储操作被传递，并且与条件存储操作相关联的存储器地址与加载在目标高速缓冲存储器片段的预留单元中的存储器地址相匹配。 广播消息协调预约单元，并方便使用较大的切片高速缓存。
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33.发明授权Method and apparatus for transporting store requests between functional units within a processor 有权用于在处理器内的功能单元之间传送存储请求的方法和装置公开(公告)号：US06477637B1
公开(公告)日：2002-11-05
申请号：US09409802
申请日：1999-09-30
IPC分类号： G06F300
CPC分类号： G06F5/08
摘要： A method and apparatus for transporting store requests between functional units within a processor is disclosed. A data processing system includes a data dispatching unit, a data receiving unit, a segmented data pipeline coupled between the data dispatching unit and the data receiving unit, and a segmented feedback line coupled between the data dispatching unit and the data receiving unit. Having multiple latches interconnected between segments, the segmented data pipeline systolically transfers data from the data dispatching unit to the data receiving unit. The segmented feedback line has multiple control latches interconnected between segments. Each of the control latches sends a control signal to a respective one of the latches in the segmented instruction pipeline to forward data to a next segment within the segmented data pipeline.
摘要翻译： 公开了一种用于在处理器内的功能单元之间传送存储请求的方法和装置。 数据处理系统包括数据调度单元，数据接收单元，耦合在数据调度单元和数据接收单元之间的分段数据流水线，以及耦合在数据调度单元和数据接收单元之间的分段反馈线。 具有在段之间互连的多个锁存器，分段数据管线将数据从数据调度单元传送到数据接收单元。 分段反馈线具有在段之间互连的多个控制锁存器。 每个控制锁存器向分段指令流水线中的锁存器中的相应一个发送控制信号，以将数据转发到分段数据流水线中的下一个段。
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34.发明授权
公开(公告)号：US5835946A
公开(公告)日：1998-11-10
申请号：US634907
申请日：1996-04-18
申请人： Michael S. Allen , Brad B. Beavers , Robert Alan Cargnoni , Jose Melanio Nunez , David W. Todd , Jen-Tian Yen
发明人： Michael S. Allen , Brad B. Beavers , Robert Alan Cargnoni , Jose Melanio Nunez , David W. Todd , Jen-Tian Yen
CPC分类号： G06F9/3004 , G06F12/0875 , G06F9/30087 , G06F12/0897
摘要： The present invention provides a system and method for efficient execution of load reserve (LARX) and store conditional (STCX) instructions in a superscalar processor. A system for efficiently providing a LARX instruction in a superscalar processor is disclosed. The system comprises a data cache (Dcache) for receiving the LARX instruction. The data cache further includes a decoder means for setting and resetting of a validation of the load reserve instruction, an internal cache for receiving address information and for providing data. The system also includes a register means for receiving the LARX instruction and a controller means for providing a physical address based upon the address information. The system provides for the validation being accomplished in one cycle for the LARX instruction when there is a hit on the internal data cache.
摘要翻译： 本发明提供了一种用于在超标量处理器中有效执行负载储备（LARX）和存储条件（STCX）指令的系统和方法。 公开了一种用于在超标量处理器中有效提供LARX指令的系统。 该系统包括用于接收LARX指令的数据高速缓存（Dcache）。 数据高速缓存还包括用于设置和重置负载保留指令的验证的解码器装置，用于接收地址信息并用于提供数据的内部高速缓存。 该系统还包括用于接收LARX指令的寄存器装置和用于基于地址信息提供物理地址的控制器装置。 当在内部数据高速缓存上存在命中时，系统提供在LARX指令的一个周期内完成的验证。
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35.发明授权Method and data processing system for processor-to-processor communication in a clustered multi-processor system 失效用于集群多处理器系统中处理器到处理器通信的方法和数据处理系统公开(公告)号：US07734877B2
公开(公告)日：2010-06-08
申请号：US11954686
申请日：2007-12-12
IPC分类号： G06F13/00
CPC分类号： G06F15/173 , H04W28/14
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译： 包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。 每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。
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36.发明申请METHOD AND DATA PROCESSING SYSTEM FOR PROCESSOR-TO-PROCESSOR COMMUNICATION IN A CLUSTERED MULTI-PROCESSOR SYSTEM 失效集成多处理器系统中处理器到处理器通信的方法和数据处理系统公开(公告)号：US20080155231A1
公开(公告)日：2008-06-26
申请号：US11954686
申请日：2007-12-12
CPC分类号： G06F15/173 , H04W28/14
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译： 包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。 每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。
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37.发明授权Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network 有权基于群集的多处理器无线网络中微处理器通信的方法和数据处理系统公开(公告)号：US07360067B2
公开(公告)日：2008-04-15
申请号：US10318513
申请日：2002-12-12
IPC分类号： G06F15/173
CPC分类号： G06F15/173 , H04W28/14
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译： 包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。 每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。
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38.发明授权Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效基于群集的多处理器系统中微处理器通信的方法和数据处理系统公开(公告)号：US07359932B2
公开(公告)日：2008-04-15
申请号：US10318516
申请日：2002-12-12
IPC分类号： G06F15/76 , G06F15/163
CPC分类号： H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译： 包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。 每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。 每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。
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39.发明授权Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system 失效用于根据数据处理系统中的推测性L2缓存命中来最优地发布依赖指令的方法和系统公开(公告)号：US06490653B1
公开(公告)日：2002-12-03
申请号：US09325397
申请日：1999-06-03
IPC分类号： G06F1208
CPC分类号： G06F9/383 , G06F9/3842
摘要： A method for optimally issuing instructions that are related to a first instruction in a data processing system is disclosed. The processing system includes a primary and secondary cache. The method and system comprises speculatively indicating a hit of the first instruction in a secondary cache and releasing the dependent instructions. The method and system includes determining if the first instruction is within the secondary cache. The method and system further includes providing data related to the first instruction from the secondary cache to the primary cache when the instruction is within the secondary cache. A method and system in accordance with the present invention causes instructions that create dependencies (such as a load instruction) to signal an issue queue (which is responsible for issuing instructions with resolved conflicts) in advance, that the instruction will complete in a predetermined number of cycles. In an embodiment, a core interface unit (CIU) will signal an execution unit such as the Load Store Unit (LSU) that it is assumed that the instruction will hit in the L2 cache. An issue queue uses the signal to issue dependent instructions at an optimal time. If the instruction misses in the L2 cache, the cache hierarchy causes the instructions to be abandoned and re-executed when the data is available.
摘要翻译： 公开了一种用于最佳地发出与数据处理系统中的第一指令相关的指令的方法。 处理系统包括主缓存和二级缓存。 所述方法和系统包括推测性地指示二次高速缓存中的第一指令的命中并释放依赖指令。 该方法和系统包括确定第一指令是否在二级高速缓存内。 所述方法和系统还包括当所述指令在所述辅助高速缓存内时，将与所述第二指令相关的数据提供给所述主缓存。 根据本发明的方法和系统预先产生依赖性（诸如加载指令）的指令来发送发出队列（其负责发出具有解决的冲突的指令），指令将以预定数量完成 的周期。 在一个实施例中，核心接口单元（CIU）将向诸如加载存储单元（LSU）的执行单元发出信号，假定该指令将在L2高速缓存中命中。 问题队列使用信号在最佳时间发出相关指令。 如果L2缓存中的指令丢失，则缓存层次结构会导致在数据可用时放弃指令并重新执行指令。
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