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    Semiconductor memory device
    35.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5374839A

    公开(公告)日：1994-12-20

    申请号：US40065

    申请日：1993-03-30

    申请人： Jun-Young Jeon ,  Hoon Choi ,  Dong-Il Seo

    发明人： Jun-Young Jeon ,  Hoon Choi ,  Dong-Il Seo

    IPC分类号： G11C5/04 ,  H01L27/105 ,  H01L27/02

    CPC分类号： H01L27/105

    摘要： A semiconductor memory device, e.g., a DRAM, which includes a P-type semiconductor substrate, a memory array each memory cell of which includes at least one N-channel MOS transistor, a CMOS peripheral circuit at least partially surrounding the memory array, the peripheral circuit including at least one P-channel MOS transistor formed in an N-type well region formed in the substrate, and at least one N-channel MOS transistor formed in the substrate outside of the N-type well region, and, a P-type minority carrier absorption semiconductor region formed in the substrate between the N-type well region and the memory array. The minority carrier absorption semiconductor region is preferably connected to a source of negative voltage, e.g., the substrate bias voltage, and a separate N-type region formed in the N-type well region is preferably connected to a source of positive voltage, e.g., the power supply voltage, Vdd, of the memory device. The N-type well region functions to absorb or capture hot electrons generated by the N-channel MOS transistor of the CMOS peripheral circuit, and the P-type minority carrier absorption semiconductor region functions to absorb or capture holes which would otherwise combine with the hot electrons to induce substrate current which could deleteriously lower the threshold voltage level of the memory cells of the memory array and thereby degrade the data storage integrity thereof.

    摘要翻译： 包括P型半导体衬底的半导体存储器件，例如DRAM，每个存储单元的存储器阵列，其存储单元包括至少一个N沟道MOS晶体管，至少部分地围绕存储器阵列的CMOS外围电路， 外围电路，包括形成在形成于衬底中的N型阱区中的至少一个P沟道MOS晶体管和形成在N型阱区外部的衬底中的至少一个N沟道MOS晶体管，以及P 型少数载流子吸收半导体区域形成在N型阱区域和存储器阵列之间的衬底中。 少数载流子吸收半导体区域优选地连接到负电压源，例如衬底偏置电压，并且形成在N型阱区域中的单独N型区域优选地连接到正电压源，例如， 存储器件的电源电压Vdd。 N型阱区域用于吸收或捕获由CMOS外围电路的N沟道MOS晶体管产生的热电子，并且P型少数载流子吸收半导体区域用于吸收或捕获否则与热结合的空穴 电子以诱导衬底电流，这可以有害地降低存储器阵列的存储器单元的阈值电压电平，从而降低其数据存储完整性。

    Delay locked loop circuit and integrated circuit including the same
    37.
    发明授权
    Delay locked loop circuit and integrated circuit including the same 有权
    延迟锁定环电路和集成电路包括相同

    公开(公告)号：US08797073B2

    公开(公告)日：2014-08-05

    申请号：US12981256

    申请日：2010-12-29

    申请人： Min-Su Park ,  Hoon Choi

    发明人： Min-Su Park ,  Hoon Choi

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814

    摘要： A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.

    摘要翻译： 延迟锁定环（DLL）电路包括定时脉冲发生单元，其被配置为响应于源时钟而在延迟移位更新周期期间产生顺序脉冲的多个定时脉冲，其中所产生的定时脉冲的数量根据 到源时钟的频率; 时钟延迟单元，被配置为将源时钟的相位与由每个定时脉冲定义的时间点的反馈时钟的相位进行比较，并且延迟对应于所述定时脉冲的上升沿或下降沿的内部时钟的相位 源时钟，根据比较结果; 以及延迟复制模型单元，被配置为反映所述时钟延迟单元的输出时钟上的内部时钟路径的实际延迟条件，并输出所述反馈时钟。

    Semiconductor memory apparatus
    38.
    发明授权
    Semiconductor memory apparatus 失效
    半导体存储装置

    公开(公告)号：US08624643B2

    公开(公告)日：2014-01-07

    申请号：US11824360

    申请日：2007-06-29

    申请人： Hoon Choi

    发明人： Hoon Choi

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812

    摘要： A semiconductor memory apparatus includes a phase comparator configured to compare phases of rising and falling feedback clocks with that of a reference clock, a delay circuit configured to delay the reference clock by a predetermined time based on a comparison result of the phase comparator to thereby generate rising and falling delayed clocks, a clock transmission block configured to invert the rising delayed clock outputted from the delay circuit when the rising and falling feedback clocks have substantially different phases, a duty compensator configured to compensate a duty ratio from outputs of the clock transmitting block to generate a delay locked clock having a compensated duty ratio, and a delay model configured to delay an output and an inverse output of the duty compensator by a modeled delay time respectively to generate the rising and falling feedback clocks.

    摘要翻译： 半导体存储装置包括相位比较器，被配置为将上升和下降反馈时钟的相位与参考时钟的相位进行比较;延迟电路，被配置为基于相位比较器的比较结果将参考时钟延迟预定时间，由此产生 上升和下降延迟时钟，时钟传输块，配置为当上升和下降反馈时钟具有实质上不同的相位时，反相从延迟电路输出的上升延迟时钟;配置为补偿占空比与时钟发送块的输出 以产生具有补偿占空比的延迟锁定时钟，以及延迟模型，被配置为分别延迟占空比补偿器的输出和反相输出模拟延迟时间以产生上升和下降反馈时钟。

    APPARATUSES AND METHODS FOR LINE CHARGE SHARING
    40.
    发明申请
    APPARATUSES AND METHODS FOR LINE CHARGE SHARING 有权
    线路充电共享的装置和方法

    公开(公告)号：US20130208547A1

    公开(公告)日：2013-08-15

    申请号：US13369928

    申请日：2012-02-09

    申请人： Hoon Choi

    发明人： Hoon Choi

    IPC分类号： G11C7/10 ,  G11C7/12

    CPC分类号： H03K19/0008 ,  G11C7/1048 ,  G11C7/12 ,  G11C8/08 ,  H03K19/0175

    摘要： Apparatuses and methods for charge sharing between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing circuit, The charge sharing circuit may be coupled to the first line and the second line and configured to receive a first data signal and a second data signal. The charge sharing circuit may be further configured to cause charge to be shared between the first line and the second line responsive, at least in part, to the first data signal and the second data signal having different logic levels.

    摘要翻译： 公开了信号线之间电荷共享的装置和方法。 示例性装置可以包括第一和第二线路以及电荷共享电路。电荷共享电路可以耦合到第一线路和第二线路并且被配置为接收第一数据信号和第二数据信号。 电荷共享电路还可以被配置为至少部分地响应于具有不同逻辑电平的第一数据信号和第二数据信号，使电荷在第一线路和第二线路之间共享。