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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5374839A

    公开(公告)日：1994-12-20

    申请号：US40065

    申请日：1993-03-30

    申请人： Jun-Young Jeon ,  Hoon Choi ,  Dong-Il Seo

    发明人： Jun-Young Jeon ,  Hoon Choi ,  Dong-Il Seo

    IPC分类号： G11C5/04 ,  H01L27/105 ,  H01L27/02

    CPC分类号： H01L27/105

    摘要： A semiconductor memory device, e.g., a DRAM, which includes a P-type semiconductor substrate, a memory array each memory cell of which includes at least one N-channel MOS transistor, a CMOS peripheral circuit at least partially surrounding the memory array, the peripheral circuit including at least one P-channel MOS transistor formed in an N-type well region formed in the substrate, and at least one N-channel MOS transistor formed in the substrate outside of the N-type well region, and, a P-type minority carrier absorption semiconductor region formed in the substrate between the N-type well region and the memory array. The minority carrier absorption semiconductor region is preferably connected to a source of negative voltage, e.g., the substrate bias voltage, and a separate N-type region formed in the N-type well region is preferably connected to a source of positive voltage, e.g., the power supply voltage, Vdd, of the memory device. The N-type well region functions to absorb or capture hot electrons generated by the N-channel MOS transistor of the CMOS peripheral circuit, and the P-type minority carrier absorption semiconductor region functions to absorb or capture holes which would otherwise combine with the hot electrons to induce substrate current which could deleteriously lower the threshold voltage level of the memory cells of the memory array and thereby degrade the data storage integrity thereof.

    摘要翻译： 包括P型半导体衬底的半导体存储器件，例如DRAM，每个存储单元的存储器阵列，其存储单元包括至少一个N沟道MOS晶体管，至少部分地围绕存储器阵列的CMOS外围电路， 外围电路，包括形成在形成于衬底中的N型阱区中的至少一个P沟道MOS晶体管和形成在N型阱区外部的衬底中的至少一个N沟道MOS晶体管，以及P 型少数载流子吸收半导体区域形成在N型阱区域和存储器阵列之间的衬底中。 少数载流子吸收半导体区域优选地连接到负电压源，例如衬底偏置电压，并且形成在N型阱区域中的单独N型区域优选地连接到正电压源，例如， 存储器件的电源电压Vdd。 N型阱区域用于吸收或捕获由CMOS外围电路的N沟道MOS晶体管产生的热电子，并且P型少数载流子吸收半导体区域用于吸收或捕获否则与热结合的空穴 电子以诱导衬底电流，这可以有害地降低存储器阵列的存储器单元的阈值电压电平，从而降低其数据存储完整性。

    Authentication apparatus and method for non-real-time IPTV system
    4.
    发明授权
    Authentication apparatus and method for non-real-time IPTV system 有权
    非实时IPTV系统的认证装置和方法

    公开(公告)号：US08769280B2

    公开(公告)日：2014-07-01

    申请号：US13170331

    申请日：2011-06-28

    申请人： Dae-Hee Seo ,  Hyeok-Chan Kwon ,  Seung-Min Lee ,  Yong-Hyuk Moon ,  Jae-Hoon Nah ,  Taek-Yong Nam ,  Dong-Il Seo

    发明人： Dae-Hee Seo ,  Hyeok-Chan Kwon ,  Seung-Min Lee ,  Yong-Hyuk Moon ,  Jae-Hoon Nah ,  Taek-Yong Nam ,  Dong-Il Seo

    IPC分类号： H04L9/32

    CPC分类号： H04L9/0869 ,  H04L9/3218 ,  H04L2209/601

    摘要： An authentication apparatus for a non-real-time IPTV system decrypts a first encrypted value included in a contents request message received from a device using a preset session key, and then verifies the validity of the contents request message. If the verification results of the contents request message are valid, the authentication apparatus encrypts a variation between timestamps of the authentication apparatus and the device using the session key, and then generates a second encrypted value. After verification information by which the device is capable of verifying the authentication apparatus has been generated using the second encrypted value, the authentication apparatus sends verification information, together with contents corresponding to the contents request message, to the device.

    摘要翻译： 用于非实时IPTV系统的认证装置使用预设会话密钥来解密从设备接收到的内容请求消息中包含的第一加密值，然后验证内容请求消息的有效性。 如果内容请求消息的验证结果有效，则认证装置使用会话密钥对认证装置的时间戳和装置的变化进行加密，然后生成第二加密值。 在使用第二加密值生成了能够验证认证装置的认证信息的认证信息之后，认证装置将与内容请求消息对应的内容的验证信息发送到设备。

    Temperature sensor instruction signal generator and semiconductor memory device having the same
    5.
    发明授权
    Temperature sensor instruction signal generator and semiconductor memory device having the same 失效
    温度传感器指令信号发生器和具有相同功能的半导体存储器件

    公开(公告)号：US07499359B2

    公开(公告)日：2009-03-03

    申请号：US11354125

    申请日：2006-02-15

    申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

    发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

    IPC分类号： G11C7/00

    CPC分类号： G01K7/01

    摘要： A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

    摘要翻译： 可以驱动温度传感器的温度传感器指令信号发生器和包括该温度传感器的半导体存储器件。 温度传感器指令信号发生器可以使用主时钟（CLK）信号，时钟使能（CKE）信号，行地址选择（RAS）信号， 列地址选择（CAS）信号，写使能（WE）信号和芯片选择（CS）信号，其中所述指令信号可以对应于自刷新模式，自动刷新模式和 长tRAS模式。 半导体存储器件可以包括温度传感器和温度传感器指令信号发生器。

    Semiconductor memory device for performing refresh operation
    7.
    发明授权
    Semiconductor memory device for performing refresh operation 有权
    用于执行刷新操作的半导体存储器件

    公开(公告)号：US07180808B2

    公开(公告)日：2007-02-20

    申请号：US10954530

    申请日：2004-09-29

    申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Young-Hun Seo

    发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Young-Hun Seo

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40622

    摘要： A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.

    摘要翻译： 根据本发明的存储器件包括多个刷新模式和刷新控制器。 第一刷新模式可以分别在包括多个块和所有存储体中的每一个的多个存储体中选择一个存储器块。 此外，第一刷新模式可以针对所选择的存储块执行刷新操作。 第二刷新模式可以选择一个存储体的一部分并执行与所选存储体的数据的刷新操作。 控制器可以在刷新操作中选择第一和第二刷新模式之一。

    Failed cell address programming circuit and method for programming failed cell address
    9.
    发明授权
    Failed cell address programming circuit and method for programming failed cell address 有权
    单元地址编程电路失败，单元地址编程失败的方法

    公开(公告)号：US06788596B2

    公开(公告)日：2004-09-07

    申请号：US10347181

    申请日：2003-01-21

    申请人： Jae-Hoon Kim ,  Dong-Il Seo ,  Hyo-Jin Oh

    发明人： Jae-Hoon Kim ,  Dong-Il Seo ,  Hyo-Jin Oh

    IPC分类号： G11C700

    CPC分类号： G11C29/785 ,  G11C29/72 ,  G11C2029/1208

    摘要： A semiconductor memory device and a failed cell address programming circuit usable therein. The semiconductor memory device as packaged includes a memory cell array having a plurality of memory cells accessed by an internal address, a plurality of redundant memory cells accessed by a failed cell address of a failed memory cell for repairing a failed memory cell, a comparator for comparing data output from the memory cells during testing the semiconductor memory device as packaged and generating a comparative correspondence signal, a mode setting register for storing an externally applied failed cell address programming control signal in response to a mode control signal, an address generating circuit for generating the internal address by buffering and latching an externally applied address, a failed cell address programming circuit for latching the internal address output from the address generating circuit in response to the failed cell address programming control signal when the comparative accordance signal indicates that a failed memory cell is detected and programming the failed cell address which is an address for accessing the failed memory cell; and a failed cell address decoding circuit for generating a redundant selection signal when the internal address output from the address generating circuit and the failed cell address output from the failed cell address programming correspond.

    摘要翻译： 半导体存储器件和可用于其中的故障单元地址编程电路。 封装的半导体存储器件包括具有由内部地址访问的多个存储器单元的存储单元阵列，由故障存储器单元的故障单元地址访问的多个冗余存储器单元，用于修复故障存储单元，比较器 比较在封装半导体存储器件的测试期间从存储器单元输出的数据，并产生比较对应信号;模式设置寄存器，用于响应于模式控制信号存储外部施加的故障单元地址编程控制信号;地址产生电路， 通过缓冲和锁存外部施加的地址来产生内部地址，一个故障的单元地址编程电路，用于当比较的一致信号指示故障存储器时，响应于故障的单元地址编程控制信号来锁存从地址产生电路输出的内部地址 单元被检测和编程t 他失败的单元地址是访问失败的存储单元的地址; 以及当从地址产生电路输出的内部地址和从故障单元地址编程输出的故障单元地址对应时，产生冗余选择信号的故障单元地址解码电路。

    Random access memory device capable of minimizing sensing noise
    10.
    发明授权
    Random access memory device capable of minimizing sensing noise 有权
    能够最小化感应噪声的随机存取存储器件

    公开(公告)号：US06337823B1

    公开(公告)日：2002-01-08

    申请号：US09612169

    申请日：2000-07-08

    申请人： Dong-Il Seo ,  Gi-Hong Kim

    发明人： Dong-Il Seo ,  Gi-Hong Kim

    IPC分类号： G11C700

    CPC分类号： G11C11/4091 ,  G11C7/06

    摘要： A dynamic random access memory device includes a circuit for generating sense amplification activation signals applied to sense amplifier circuits. The circuit changes the slopes of the activation signals according to variation of a power supply voltage. According to the present invention, the peak current the sense amplifier circuits use when the power supply voltage increases, is reduced, so that the sense amplifier circuits create less noise in the memory device.

    摘要翻译： 动态随机存取存储器件包括用于产生施加到读出放大器电路的读出放大激活信号的电路。 该电路根据电源电压的变化改变激活信号的斜率。 根据本发明，当电源电压增加时，读出放大器电路使用的峰值电流被减小，使得读出放大器电路在存储器件中产生较少的噪声。