公开(公告)号：US10475804B1

公开(公告)日：2019-11-12

申请号：US16019821

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Shinsuke Yada ,  Yanli Zhang

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/423 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a drain-select-level electrically conductive layer located over the alternating stack. Memory stack structures extend through the alternating stack and the drain-select-level electrically conductive layer. Dielectric divider structures including a respective pair of straight sidewalls and drain-select-level isolation structures including a respective pair of sidewalls that include a respective set of concave vertical sidewall segments divide the drain-select-level electrically conductive layer into multiple strips. The drain-select-level electrically conductive layer and the drain-select-level isolation structures are formed by replacement of a drain-select-level sacrificial material layer with a conductive material and by replacement of drain-select-level sacrificial line structures with dielectric material portions.

公开(公告)号：US11587943B2

公开(公告)日：2023-02-21

申请号：US17009374

申请日：2020-09-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Akio Nishida

IPC: H01L25/065 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/538 ,  H01L23/00

Abstract: A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures. External bonding pads may be subsequently formed.

公开(公告)号：US11189335B2

公开(公告)日：2021-11-30

申请号：US16683209

申请日：2019-11-13

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C11/408 ,  G11C7/14 ,  G11C11/4094 ,  H01L27/06 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/4091

Abstract: A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.

公开(公告)号：US20210173559A1

公开(公告)日：2021-06-10

申请号：US16704729

申请日：2019-12-05

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze

IPC: G06F3/06 ,  G06F13/16 ,  G11C16/24 ,  G11C16/14

Abstract: A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.

公开(公告)号：US10991705B2

公开(公告)日：2021-04-27

申请号：US16556854

申请日：2019-08-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Jayavel Pachamuthu

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.

公开(公告)号：US10797062B1

公开(公告)日：2020-10-06

申请号：US16385010

申请日：2019-04-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Akio Nishida

IPC: H01L25/065 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/538 ,  H01L23/00

Abstract: A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures. External bonding pads may be subsequently formed.

公开(公告)号：US10756106B2

公开(公告)日：2020-08-25

申请号：US16202713

申请日：2018-11-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Michiaki Sano ,  Ken Oowada ,  Zhixin Cui

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/8234 ,  H01L27/11524 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.

公开(公告)号：US10741579B2

公开(公告)日：2020-08-11

申请号：US16215912

申请日：2018-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Ken Oowada

IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L23/528 ,  H01L21/311 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/36 ,  H01L21/306

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.

公开(公告)号：US10741535B1

公开(公告)日：2020-08-11

申请号：US16275668

申请日：2019-02-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze

IPC: H01L25/065 ,  G11C16/04 ,  H01L23/00 ,  H01L25/18 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556

Abstract: A first memory die includes an array of first memory stack structures and first bit lines. A second memory die includes an array of second memory stack structures and second bit lines electrically connected to a respective subset of the second drain regions. A support die is provided, which includes a peripheral circuitry for operating the array of first memory stack structures and the array of second memory stack structures. The peripheral circuitry includes a plurality of sense amplifiers configured to make switchable electrical connections to a set of bit lines selected from the first bit lines and the second bit lines. The first memory die is bonded to the support die, and the second memory die is bonded to the first memory die. The peripheral circuitry in the support die may be shared between the first memory die and the second memory die.

公开(公告)号：US10700078B1

公开(公告)日：2020-06-30

申请号：US16278488

申请日：2019-02-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Yanli Zhang

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/11575 ,  H01L27/11578 ,  H01L21/28

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.