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    Low latency filter
    32.
    发明授权
    Low latency filter 有权
    低延迟过滤器

    公开(公告)号：US08878710B2

    公开(公告)日：2014-11-04

    申请号：US13677674

    申请日：2012-11-15

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankur Bal ,  Neha Bhargava ,  Anupam Jain

    IPC: H03M3/00 ,  H03M1/12

    CPC classification number: H03M3/30 ,  H03M3/344 ,  H03M3/376 ,  H03M3/462

    Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.

    Abstract translation: 在一个实施例中，对一组输入样本进行滤波，以使用N抽头滤波器提供一组滤波样本。 N抽头滤波器的稳态响应输出样本由滤波样本集合的第N / 2个样本确定。

    Timing skew mismatch calibration for time interleaved analog to digital converters
    33.
    发明授权
    Timing skew mismatch calibration for time interleaved analog to digital converters 有权

    公开(公告)号：US12009830B2

    公开(公告)日：2024-06-11

    申请号：US18075977

    申请日：2022-12-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankur Bal ,  Vikram Singh

    IPC: H03M1/10 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12

    CPC classification number: H03M1/1023 ,  H03M1/0624 ,  H03M1/0836 ,  H03M1/1215

    Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

    High frequency resolution digital sinusoid generator
    34.
    发明授权
    High frequency resolution digital sinusoid generator 有权

    公开(公告)号：US11689191B2

    公开(公告)日：2023-06-27

    申请号：US17673214

    申请日：2022-02-16

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankur Bal

    IPC: H03K5/00 ,  H03K5/02

    CPC classification number: H03K5/02 ,  H03K2005/00078

    Abstract: A delay circuit applies a one sample delay to a first digital sinusoid signal and outputs a delayed digital sinusoid signal. The first digital sinusoid signal and the delayed digital sinusoid signal are then added to each other by an adder circuit to generate an added digital sinusoid signal. A gain scaling circuit applies a scaling factor to the added digital sinusoid signal to generate a second digital sinusoid signal. Samples of the first and second digital sinusoid signals are alternately selected by a multiplexing circuit to generate a third digital sinusoid signal having twice as many samples as the first digital sinusoid signal over a same sinusoid period.

    High speed data weighted averaging (DWA) to binary converter circuit
    35.
    发明授权
    High speed data weighted averaging (DWA) to binary converter circuit 有权

    公开(公告)号：US11563443B2

    公开(公告)日：2023-01-24

    申请号：US17374351

    申请日：2021-07-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankur Bal ,  Rupesh Singh

    IPC: H03M1/66 ,  H03K3/356 ,  G06F5/01 ,  H03M1/68

    Abstract: A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.

    Clock and data recovery circuit
    37.
    发明授权
    Clock and data recovery circuit 有权

    公开(公告)号：US11411565B2

    公开(公告)日：2022-08-09

    申请号：US17131917

    申请日：2020-12-23

    Applicant: STMicroelectronics International N.V.

    Inventor： Rupesh Singh ,  Ankur Bal

    IPC: H03L7/08 ,  G06F1/04 ,  H03L7/091

    Abstract: A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.

    Debounce circuit with noise immunity and glitch event tracking
    38.
    发明授权
    Debounce circuit with noise immunity and glitch event tracking 有权

    公开(公告)号：US11177799B2

    公开(公告)日：2021-11-16

    申请号：US17029631

    申请日：2020-09-23

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankur Bal ,  Vikas Chelani

    IPC: H03K5/1252 ,  H03K19/003 ,  H03K17/16

    Abstract: A debounce circuit and a method for masking or filtering a glitch from an input signal are provided. The debounce circuit includes a reset synchronizer circuit and a logic circuit. The reset synchronizer circuit receives the input signal, detects a glitch in the input signal and outputs one or more reset synchronizer output signals having a first reset synchronizer state indicating detection of the glitch. The logic circuit receives the one or more reset synchronizer output signals, determines that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating detection of the glitch and in response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, keeps an output signal of the debounce circuit in a present state of the output signal of the debounce circuit.

    Programmable delay circuit
    40.
    发明授权
    Programmable delay circuit 有权

    公开(公告)号：US10944387B2

    公开(公告)日：2021-03-09

    申请号：US16896463

    申请日：2020-06-09

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankur Bal ,  Jeet Narayan Tiwari

    IPC: H03K5/133 ,  H03K5/1534 ,  H03K3/027 ,  H03K21/08 ,  H03K5/00

    Abstract: A delay line includes a delay chain, a pulse generator generating a pulse based on a received input signal, and a delay chain control circuit. The delay chain control circuit has a first input receiving the pulse, a second input receiving output from a last element of the delay chain, and a selection input receiving a delayed version of the received input signal. The delay chain control circuit has an output coupled to provide input to a first element of the delay chain in response to the delayed version of the received input signal. An output selection circuit receives outputs from each element of the delay chain, counts assertions of the output of the last element of the delay chain and, in response to the count being equal to a desired count, passes a desired one of the outputs of the elements of the delay chain as output.

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