公开(公告)号：US20180114756A1

公开(公告)日：2018-04-26

申请号：US15851467

申请日：2017-12-21

Applicant: STMicroelectronics, Inc.

Inventor： John H. ZHANG ,  Walter KLEEMEIER ,  Paul FERREIRA ,  Ronald K. SAMPSON

IPC: H01L23/544 ,  H01L21/66 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

公开(公告)号：US20180040554A1

公开(公告)日：2018-02-08

申请号：US15785931

申请日：2017-10-17

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0676 ,  H01L27/0682 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

公开(公告)号：US20170011971A1

公开(公告)日：2017-01-12

申请号：US15276516

申请日：2016-09-26

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG ,  Chengyu NIU ,  Heng YANG

IPC: H01L21/8238 ,  H01L27/092

Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

Abstract translation: 增强载流子迁移率的方法和装置。 集成电路可以包括两种类型的半导体器件。 第一类型的装置可以包括金属门和以第一方式应变的通道。 第二类型的装置可以包括金属门和以第二方式应变的通道。 这些门可以共同地包括三种或更少的金属材料。 门可以共享相同的金属材料。 在集成电路上形成半导体器件的方法可以包括分别在对应于第一和第二栅极的集成电路的第一和第二区域中沉积第一和第二金属层。

公开(公告)号：US20160293756A1

公开(公告)日：2016-10-06

申请号：US14675298

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/78 ,  H01L29/267 ,  H01L29/165 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/785

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

Abstract translation: 使用FinFET器件架构，在硅中实现隧道晶体管。 隧道FinFET具有非平面的垂直结构，其从形成在硅衬底中的掺杂漏极的表面延伸出来。 垂直结构包括由减法蚀刻工艺限定的轻掺杂的鳍，以及通过外延生长形成在鳍的顶部上的重掺杂源。 漏极和沟道具有相似的极性，与源极相反。 栅极邻接通道区域，电容地控制从相对侧通过通道的电流。 源极，漏极和栅极端子都可以通过在器件完成之后形成的前侧触点电可访问。 隧道FinFET的制造与常规CMOS制造工艺兼容，包括替换金属栅极和自对准接触工艺。 与传统的平面器件相比，低功耗操作允许隧道FinFET提供高电流密度。

公开(公告)号：US20160293371A1

公开(公告)日：2016-10-06

申请号：US14675359

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01H59/00 ,  H01H11/00

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.