公开(公告)号：US20210041727A1

公开(公告)日：2021-02-11

申请号：US17083525

申请日：2020-10-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Frédéric Boeuf

IPC: G02F1/025 ,  H01L29/66

Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.

公开(公告)号：US10823986B2

公开(公告)日：2020-11-03

申请号：US16254798

申请日：2019-01-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Frédéric Boeuf

IPC: G02F1/035 ,  G02F1/025 ,  H01L29/66

Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.

公开(公告)号：US10684251B2

公开(公告)日：2020-06-16

申请号：US15631078

申请日：2017-06-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Getenet Tesega Ayele ,  Stephane Monfray

IPC: G01N27/414

Abstract: A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage having a first magnitude and a first polarity for application to the first bias voltage node. The bias voltage generator circuit is further configured to generate a control gate voltage having a second magnitude and a second polarity for application to the second bias voltage node. The second polarity is opposite the first polarity.

公开(公告)号：US10074649B2

公开(公告)日：2018-09-11

申请号：US15251009

申请日：2016-08-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Gaspard Hiblot

IPC: H01L27/07 ,  G01N27/414 ,  H01L27/06 ,  H01L29/423 ,  G01R19/165 ,  G01N33/49

CPC classification number: H01L27/0722 ,  G01N27/414 ,  G01N27/4145 ,  G01N33/49 ,  G01R19/16519 ,  H01L27/0623 ,  H01L27/0705 ,  H01L27/1207 ,  H01L29/42356

Abstract: An integrated electronic detector operates to detecting a variation in potential on an input terminal. The detector includes a MOS transistor having a drain forming an output. Variation in drain current is representative of the variation in potential. A bipolar transistor has a base forming the input terminal and a collector electrically connected to the gate of the MOS transistor. The detector has a first configuration in which the bipolar transistor is conducting and the MOS transistor is turned off. The detector has a second configuration in which the bipolar transistor is turned off and the MOS transistor is in a sub-threshold operation. Transition of the detector from the first configuration to the second configuration occurs in response to the variation in potential.

公开(公告)号：US09601381B2

公开(公告)日：2017-03-21

申请号：US14097565

申请日：2013-12-05

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Loubet ,  Stephane Monfray ,  Ronald Kevin Sampson

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/84 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer. Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

公开(公告)号：US20160351661A1

公开(公告)日：2016-12-01

申请号：US14962193

申请日：2015-12-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Thomas Skotnicki

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/76264 ,  H01L29/0692 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78696

Abstract: An integrated circuit includes a substrate with an isolation region that bounds a zone. A transistor includes a concave semiconductor region that is supported by the isolation region in a first direction and has a concavity turned to face towards the zone. The concave semiconductor region contains drain, source and channel regions. A gate region for the transistor possesses a concave portion overlapping a portion of the concave semiconductor region. A dielectric region is located between the zone of the substrate and the concave semiconductor region.

Abstract translation: 集成电路包括具有限定区域的隔离区域的衬底。 晶体管包括凹形半导体区域，该半导体区域在第一方向上由隔离区域支撑并且具有朝向该区域的凹面。 凹入半导体区域包含漏极，源极和沟道区域。 晶体管的栅极区域具有与凹入半导体区域的一部分重叠的凹部。 电介质区域位于衬底的区域和凹形半导体区域之间。

公开(公告)号：US20160241168A1

公开(公告)日：2016-08-18

申请号：US15042293

申请日：2016-02-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  SOCPRA Sciences et Génie S.E.C.

Inventor： Gholamreza Mirshekari ,  Etienne Leveille ,  Luc Guy Frechette ,  Stephane Monfray ,  Thomas Skotnicki

IPC: H02N2/18

CPC classification number: H02N2/18

Abstract: A first closed enclosure defines a cavity having an inner dimension smaller than 5 mm. At least one second resiliently deformable closed enclosure is connected in fluid communication with the first enclosure. A fluid at more than 90% in the liquid state fills the first and second enclosures. A first portion of the first enclosure is in contact with a hot source of a temperature higher than the evaporation temperature of the fluid. A second portion of the first enclosure located between the first portion and the resiliently deformable closed enclosure is in contact with a cold source at a temperature lower than the condensation temperature of the fluid. An electromechanical transducer is coupled to a deformable membrane of the resiliently deformable closed enclosure.

Abstract translation: 第一封闭的外壳限定了具有小于5mm的内部尺寸的空腔。 至少一个第二可弹性变形的封闭外壳与第一外壳流体连通地连接。 在液体状态下超过90％的流体填充第一和第二外壳。 第一外壳的第一部分与高于流体蒸发温度的温度的热源接触。 位于第一部分和可弹性变形的封闭外壳之间的第一外壳的第二部分在低于流体冷凝温度的温度下与冷源接触。 机电换能器联接到可弹性变形的封闭外壳的可变形膜。

公开(公告)号：US11644697B2

公开(公告)日：2023-05-09

申请号：US16988480

申请日：2020-08-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sébastien Cremer ,  Frédéric Boeuf ,  Stephane Monfray

IPC: G02F1/01 ,  G02F1/035 ,  G02B6/12

CPC classification number: G02F1/035 ,  G02B6/12004 ,  G02F1/0147 ,  G02F2201/063

Abstract: The present disclosure relates to a method comprising the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.

公开(公告)号：US20210055579A1

公开(公告)日：2021-02-25

申请号：US16988480

申请日：2020-08-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sébastien Cremer ,  Frédéric Boeuf ,  Stephane Monfray

IPC: G02F1/035

Abstract: The present disclosure relates to a method comprising the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.

公开(公告)号：US10794856B2

公开(公告)日：2020-10-06

申请号：US16275051

申请日：2019-02-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Getenet Tesega Ayele ,  Stephane Monfray

IPC: G01N27/414 ,  H01L23/522 ,  G01N27/416 ,  H01L21/768 ,  H01L29/423

Abstract: A detection stage of an electronic detection device, for example a pH meter, includes an insulating region that receives an element to be analyzed. The insulating region is positioned on a sensing conductive region. A biasing stage includes an electrically conductive region which is capacitively coupled to the conductive region. The electrically conductive region is formed in an uppermost metallization level along with a further conductive region. That further conductive region is electrically connected to the sensing conductive region by a via passing through an insulating layer which insulates the electrically conductive region from the sensing conductive region.