公开(公告)号：US12063775B2

公开(公告)日：2024-08-13

申请号：US18484906

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H10B20/00 ,  H01L23/00 ,  G11C16/04

CPC classification number: H10B20/367 ,  G11C16/0466 ,  H01L23/57

Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

公开(公告)号：US20240040781A1

公开(公告)日：2024-02-01

申请号：US18484906

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H10B20/00

CPC classification number: H10B20/367 ,  H01L23/57

Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

公开(公告)号：US11710711B2

公开(公告)日：2023-07-25

申请号：US17351930

申请日：2021-06-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart

IPC: H01L23/00 ,  G06F21/87 ,  H04N19/44 ,  H01L27/02 ,  G06F21/75

CPC classification number: H01L23/576 ,  G06F21/75 ,  G06F21/87 ,  H01L23/57 ,  H01L27/0207 ,  H04N19/44

Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

公开(公告)号：US10754618B2

公开(公告)日：2020-08-25

申请号：US16035798

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Benoit Froment ,  Sebastien Petitdidier ,  Mathieu Lisart ,  Jean-Marc Voisin

IPC: G06F7/58 ,  H01L21/768 ,  G06F21/70 ,  H04L9/08

Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.

公开(公告)号：US20190034168A1

公开(公告)日：2019-01-31

申请号：US16035798

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Benoit Froment ,  Sebastien Petitdidier ,  Mathieu Lisart ,  Jean-Marc Voisin

IPC: G06F7/58 ,  G06F21/70 ,  H01L21/768

CPC classification number: G06F7/588 ,  G06F21/70 ,  H01L21/76829 ,  H04L9/0866

Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.

公开(公告)号：US10079215B2

公开(公告)日：2018-09-18

申请号：US15789362

申请日：2017-10-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Mathieu Lisart ,  Jimmy Fort

IPC: H01L23/00 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L23/576 ,  H01L21/762 ,  H01L27/088

Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.

公开(公告)号：US20180145039A1

公开(公告)日：2018-05-24

申请号：US15596772

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L23/28 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L23/57 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/28 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/573

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.

公开(公告)号：US20170092600A1

公开(公告)日：2017-03-30

申请号：US15072209

申请日：2016-03-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Nicolas Borrel

IPC: H01L23/00 ,  H03K17/687

CPC classification number: H01L23/576 ,  G01R31/2851 ,  G01R31/44 ,  G06F21/6245 ,  H01L22/34 ,  H01L23/647 ,  H03K17/687

Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.

公开(公告)号：US20160182225A1

公开(公告)日：2016-06-23

申请号：US15056844

申请日：2016-02-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: H04L9/08 ,  G06F12/14 ,  G06F3/06

CPC classification number: H04L9/088 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/1408 ,  G06F21/62 ,  G06F21/77 ,  G06F21/78 ,  G06F2212/402

Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.

Abstract translation: 公开了一种用于处理存储在部件上的内容的方法。 利用第一加密密钥对第一存储器的第一分区进行加密，并且用第二加密密钥对第一存储器的第二分区进行加密。 第二加密密钥与第一加密密钥不同。 第一加密密钥存储在组件的存储寄存器中，第二加密密钥存储在非易失性存储器的第一位置。 第一位置的存储器地址存储在第一存储器的第一分区中。

公开(公告)号：US09223368B2

公开(公告)日：2015-12-29

申请号：US14446814

申请日：2014-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Fabrice Marinet

IPC: G06F17/50 ,  G06F1/26 ,  G06F21/72 ,  G06K19/073 ,  H04L9/00 ,  H01L21/762 ,  H03K3/84 ,  H03K19/003 ,  H01L23/00

CPC classification number: G06F1/26 ,  G06F21/72 ,  G06K19/07309 ,  H01L21/76224 ,  H01L23/576 ,  H01L2924/0002 ,  H03K3/84 ,  H03K19/003 ,  H04L9/004 ,  H04L2209/12 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.

Abstract translation: 本公开涉及一种电子微电路中的对策方法，包括由微电路的电路执行的连续处理阶段，以及根据为该电路产生的随机值调整电路与电路的接地端之间的电源电压 处理阶段，在电路执行的每个处理阶段。