公开(公告)号：US09948193B2

公开(公告)日：2018-04-17

申请号：US15178822

申请日：2016-06-10

Applicant: STMicroelectronics S.r.l.

Inventor： Egidio Ragonese ,  Nunzio Spina ,  Pierpaolo Lombardo ,  Nunzio Greco ,  Alessandro Parisi ,  Giuseppe Palmisano

IPC: H02M3/335

CPC classification number: H02M3/33553 ,  H01L2224/48137 ,  H02M3/33523 ,  H02M3/33584 ,  H02M2001/0012

Abstract: A galvanic isolation is provided between a first circuit and a second circuit. A first galvanically isolated link is configured to transfer power from a first circuit to a second circuit across the galvanic isolation. A second galvanically isolated link is configured to feed back an error signal from the second circuit to the first circuit across the galvanic isolation for use in regulating the power transfer and further configured to support bidirectional data communication between the first and second circuits across the galvanic isolation.

公开(公告)号：US09820141B2

公开(公告)日：2017-11-14

申请号：US15279765

申请日：2016-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： Ranieri Guerra ,  Roberto Larosa ,  Giuseppe Palmisano

IPC: H04B7/00 ,  H04B1/06 ,  H04W8/22 ,  H04B17/318

CPC classification number: H04W8/22 ,  H03D1/2218 ,  H04B1/1615 ,  H04B17/318 ,  H04W52/0245

Abstract: A receiver for digital signals includes a radiofrequency stage. A feedback loop controls an amplitude of a modulated radiofrequency signal passing through the radiofrequency stage as a function of a comparison of a baseband signal with a reference value. A baseband stage includes an RC network cascaded to the radiofrequency stage and coupled to a baseband detector that generates the baseband signal. The feedback loop includes a circuit for detecting a range of variation of the comparison. The amplitude of the modulated radiofrequency signal is controlled as a function of an end value (e.g., maximum or minimum) of the detected range of variation. A switching circuit operates to selectively short circuit a resistive component of the RC network during receiver start-up.

公开(公告)号：US20160094378A1

公开(公告)日：2016-03-31

申请号：US14829775

申请日：2015-08-19

Applicant: STMicroelectronics S.r.l.

Inventor： Ranieri Guerra ,  Giuseppe Palmisano

IPC: H04L27/36 ,  H04L7/00

CPC classification number: H04L27/364 ,  H03B19/14 ,  H03B21/025 ,  H03D7/165 ,  H04L7/0091 ,  H04L27/366

Abstract: A calibration signal is generated from a modulating signal having a first frequency and a carrier signal having a second frequency. A single-sideband mixer modulates the modulating signal on the carrier signal. At least two frequency dividers by two connected in cascade receive the modulating signal modulated on the carrier signal and generate an output of the calibration signal.

Abstract translation: 从具有第一频率的调制信号和具有第二频率的载波信号产生校准信号。 单边带混频器调制载波信号上的调制信号。 串联连接的至少两个分频器接收在载波信号上调制的调制信号，并产生校准信号的输出。

公开(公告)号：US20160072435A1

公开(公告)日：2016-03-10

申请号：US14942200

申请日：2015-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： Giuseppe Palmisano ,  Nunzio Spina ,  Egidio Ragonese ,  Vincenzo Fiore

IPC: H03B5/12

CPC classification number: H03B5/1212 ,  H03B1/02 ,  H03B5/02 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03B27/00 ,  H03B2200/0074 ,  H03B2200/0076 ,  H03B2200/0078

Abstract: An oscillator circuit includes first and second oscillators arranged in a series configuration between a supply voltage node and a reference voltage node. The first and second oscillators are configured to receive a synchronizing signal for controlling synchronization in frequency and phase. An electromagnetic network provided to couple the first and the second oscillators includes a transformer with a primary circuit and a secondary circuit. The primary circuit includes a first portion coupled to the first oscillator and second portion coupled to the second oscillator. The first and second portions are connected by a circuit element for reuse of current between the first and second oscillators. The oscillator circuit is fabricated as an integrated circuit device wherein the electromagnetic network is formed in metallization layers of the device. The secondary circuit generates an output power combining power provided from the first and second portions of the primary circuit.

Abstract translation: 振荡器电路包括在电源电压节点和参考电压节点之间以串联配置布置的第一和第二振荡器。 第一和第二振荡器被配置为接收用于控制频率和相位同步的同步信号。 提供用于耦合第一和第二振荡器的电磁网络包括具有初级电路和次级电路的变压器。 主电路包括耦合到第一振荡器的第一部分和耦合到第二振荡器的第二部分。 第一和第二部分由用于在第一和第二振荡器之间重新使用电流的电路元件连接。 振荡器电路被制造为集成电路器件，其中电磁网络形成在器件的金属化层中。 次级电路产生从主电路的第一和第二部分提供的输出功率组合功率。

公开(公告)号：US08792845B2

公开(公告)日：2014-07-29

申请号：US13903679

申请日：2013-05-28

Applicant: STMicroelectronics S.r.l.

Inventor： Giuseppina Sapone ,  Alessandro Italia ,  Egidio Ragonese ,  Giuseppe Palmisano

IPC: H04B1/16 ,  H04B1/26 ,  H03B5/12

CPC classification number: H03B5/1231 ,  H03B5/1218 ,  H03B5/1243 ,  H03B5/1296 ,  H03L7/099 ,  H04B1/26

Abstract: An oscillator is described, comprising at least one transistor having a first terminal connected to a power supply voltage. The oscillator comprises at least one inductive element connected to a second terminal of the transistor and to a bias voltage and at least one capacitive element coupled between a third terminal of the transistor and ground. The oscillator further comprises means to collect the output signal of the oscillator on the second terminal of the transistor. The oscillator is of the millimeter wave type, i.e., both the inductive element and the capacitive element are sized such that the oscillation frequency is between 30 and 300 gigahertz.

Abstract translation: 描述了一种振荡器，其包括至少一个具有连接到电源电压的第一端子的晶体管。 振荡器包括连接到晶体管的第二端子和偏置电压的至少一个感应元件以及耦合在晶体管的第三端子与地之间的至少一个电容元件。 振荡器还包括在晶体管的第二端子处收集振荡器的输出信号的装置。 振荡器是毫米波型的，即感应元件和电容元件的尺寸使得振荡频率在30和300千兆赫之间。

公开(公告)号：US12081253B2

公开(公告)日：2024-09-03

申请号：US18352424

申请日：2023-07-14

Applicant: STMicroelectronics S.r.l.

Inventor： Nunzio Spina ,  Giuseppe Palmisano ,  Alessandro Castorina

IPC: H04B1/16 ,  H03F3/19 ,  H03F3/24 ,  H04L27/06

CPC classification number: H04B1/16 ,  H03F3/19 ,  H03F3/245 ,  H04L27/06 ,  H03F2200/451

Abstract: A method for calibrating the DC operating point of a PWM receiver circuit is disclosed. The PWM receiving circuit includes an envelope detector having a first resistor string, and includes a bias circuit having a second resistor string and a plurality of switches. The second resistor string is coupled between a supply voltage and a reference voltage and functions as a voltage divider. Each switch, when closed, accesses a second voltage at a node of the second resistor string connected to the closed switch. To perform the calibration process, the plurality of switches is closed one at a time, and the second voltage is compared with a first voltage at a first node of the first resistor string. The switch that, when closed, produces the smallest difference between the first voltage and the second voltage remains closed after the calibration process, and is used for demodulating the PWM signal.

公开(公告)号：US11959995B2

公开(公告)日：2024-04-16

申请号：US17395080

申请日：2021-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Finocchiaro ,  Alessandro Parisi ,  Andrea Cavarra ,  Giuseppe Papotto ,  Giuseppe Palmisano

IPC: G01S13/34 ,  G01S13/931 ,  H03B5/12 ,  H03L7/193 ,  G01S13/00

CPC classification number: G01S13/34 ,  G01S13/931 ,  H03B5/1231 ,  H03L7/193

Abstract: A PLL has a tunable resonator including an inductance and variable capacitance coupled between first and second nodes, and capacitances coupleable between the nodes. A control node is coupled to the variable capacitance and receives a control signal for tuning the resonator. A biasing circuit biases the resonator to generate an output. A PFD circuit senses timing offset of the output with respect to a reference and asserts first or second digital signals dependent on the sign of the timing offset. A charge pump generates the control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and de-asserts the timing signal after a time interval. A calibrator couples selected capacitances between the first and second nodes as a function of the second digital signal, in response to assertion of the timing signal.

公开(公告)号：US11879963B2

公开(公告)日：2024-01-23

申请号：US18108993

申请日：2023-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Parisi ,  Andrea Cavarra ,  Alessandro Finocchiaro ,  Giuseppe Papotto ,  Giuseppe Palmisano

IPC: G01S13/58 ,  G01S13/931 ,  H03B5/12 ,  H03L7/193 ,  H03L7/10 ,  G01S7/40 ,  H03L7/099

CPC classification number: G01S13/584 ,  G01S7/4056 ,  G01S13/931 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1293 ,  H03L7/099 ,  H03L7/101 ,  H03L7/103 ,  H03L7/193

Abstract: Disclosed herein is a tunable resonant circuit including an inductance directly electrically connected in series between first and second nodes, a variable capacitance directly electrically connected between the first and second nodes, and a set of switched capacitances coupled between the first and second nodes. The set of switched capacitances includes a plurality of capacitance units, each capacitance unit comprising a first capacitance for that capacitance unit directly electrically connected between the first node and a switch and a second capacitance for the capacitance unit directly electrically connected between the switch and the second node. Control circuitry is configured to receive an input control signal and connected to control the switches of the set of switched capacitances. A biasing circuit is directly electrically connected to the tunable resonance circuit at the first and second nodes.

公开(公告)号：US10917091B2

公开(公告)日：2021-02-09

申请号：US16371919

申请日：2019-04-01

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Parisi ,  Nunzio Greco ,  Nunzio Spina ,  Egidio Ragonese ,  Giuseppe Palmisano

IPC: H03K7/08 ,  H03K17/691 ,  H03K17/723 ,  H03K17/722 ,  H03B5/06 ,  H03L7/08 ,  H03L7/06 ,  H03L7/183 ,  H02M3/335 ,  H02M1/00 ,  H01F19/08

Abstract: An oscillator is coupled to a first side of a galvanic barrier for supplying thereto an electric supply signal. The oscillator is configured to be alternatively turned on and off as a function of a PWM drive signal applied thereto. A receiver circuit coupled to the galvanic barrier receives therefrom a PWM power control signal. A signal reconstruction circuit coupled between the receiver circuit block and the oscillator provides to the oscillator a PWM drive signal reconstructed from the PWM power control signal. The signal reconstruction circuit includes a PLL circuit coupled to the receiver circuit block and configured to lock to the PWM control signal from the receiver circuit block. A PLL loop within the PLL circuit is sensitive to the PWM drive signal applied to the oscillator. The PLL loop is configured to be opened as a result of the power supply oscillator being turned off.

公开(公告)号：US10193581B2

公开(公告)日：2019-01-29

申请号：US15468306

申请日：2017-03-24

Applicant: STMicroelectronics S.r.l.

Inventor： Egidio Ragonese ,  Nunzio Spina ,  Alessandro Parisi ,  Pierpaolo Lombardo ,  Nunzio Greco ,  Giuseppe Palmisano

IPC: H04B1/10 ,  H01F19/04 ,  H03F3/45 ,  H04L25/02 ,  H01F19/08

Abstract: A galvanic isolation circuit is formed by a differential transformer having primary and secondary windings for transmission of signals over a carrier between the primary and the secondary windings of the transformer. A galvanic isolation oxide layer is provide between the primary and secondary windings. Each winding includes include a center tap providing a low-impedance paths for dc and low frequency components of common-mode currents through the differential transformer. A pass-band stage is coupled to the secondary winding of the transformer and configured to permit propagation of signals over said carrier through the pass-band amplifier stage while providing for a rejection of common-mode noise.