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公开(公告)号：US20180108405A1
公开(公告)日：2018-04-19
申请号：US15842347
申请日：2017-12-14
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Francesco Perroni , Carmelo Paolino , Salvatore Polizzi
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C17/18 , G11C2013/0042
Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.
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32.发明申请公开(公告)号：US20170117051A1
公开(公告)日：2017-04-27
申请号：US15212208
申请日：2016-07-16
Applicant: STMicroelectronics S.r.l
Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.
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33.发明授权公开(公告)号：US09613712B1
公开(公告)日：2017-04-04
申请号：US15212208
申请日：2016-07-16
Applicant: STMicroelectronics S.r.l
Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.
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