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公开(公告)号：US12130360B2
公开(公告)日：2024-10-29
申请号：US18178110
申请日：2023-03-03
Applicant: STMicroelectronics S.r.l.
Inventor： Antonio Davide Leone , Vanni Poletto
CPC classification number: G01S15/931 , G01S7/521 , G01S7/524 , G01S2007/52007 , G01S2015/937 , H04R17/00
Abstract: In accordance with an embodiment, an ultrasound transmitter device includes a transformer comprising a secondary winding configured to be coupled to a piezoelectric transducer; a plurality of transistors coupled to the primary winding of the transformer and to a ground terminal via a sense resistor; an amplifier having an output coupled to control nodes of the plurality of transistors, a first input coupled to the sense resistor, and second input coupled to a reference resistor; a switching circuit configured to alternately couple control nodes of the plurality of transistors to an output of amplifier and to a reference node via complementary pulse signals, wherein the switching circuit is configured to turn on and turn off the plurality of transistors and operate the plurality of transistors in a push-pull manner; and a digital-to-analog converter having an output coupled to the reference resistor.
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公开(公告)号：US11894657B2
公开(公告)日：2024-02-06
申请号：US17360381
申请日：2021-06-28
Inventor： Romeo Letor , Vanni Poletto , Antoine Pavlin , Nadia Lecci , Alfio Russo
CPC classification number: H01S5/06216 , H01S5/0261 , H03K5/07
Abstract: An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.
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公开(公告)号：US20230324475A1
公开(公告)日：2023-10-12
申请号：US18335511
申请日：2023-06-15
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
CPC classification number: G01R31/64 , G01R27/2605 , G01R31/006
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号：US11742789B2
公开(公告)日：2023-08-29
申请号：US17535176
申请日：2021-11-24
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Vanni Poletto , Paolo Vilmercati , Marco Cignoli
CPC classification number: H02P27/12 , H02P27/085
Abstract: In an embodiment, an electronic circuit includes: a controller configured to produce a pulse-width-modulated (PWM) signal to control a first current of an electrical load; a redundant current measurement circuit configured to measure the first current and provide first and second current measurement signal; a monitor circuit coupled to the redundant current measurement circuit, the monitor circuit configured to assert a current monitor signal in response to the first and second current measurement signals being found to be matching with each other, wherein the monitor circuit is configured to: detect an absence of the asserted current monitor signal prior to expiry of a threshold time interval, and in response to detecting the absence of the asserted current monitor signal, force the controller to produce, prior to expiry of the threshold time interval, a first PWM signal pulse having a controlled duty-cycle.
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公开(公告)号：US20230055745A1
公开(公告)日：2023-02-23
申请号：US17407747
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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Patent Agency Ranking
公开(公告)号：US11150279B2
公开(公告)日：2021-10-19
申请号：US16554248
申请日：2019-08-28
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Vanni Poletto , Riccardo Miglierina , Antonio Davide Leone , Sergio Lecce
IPC: G01R31/34 , G01R19/165 , G11C27/02 , H03F3/45
Abstract: A circuit includes a switching circuit including a first switch and a second switch. A current sensing circuit is coupled to the switching circuit to sense a first current through the first switch and to generate a first sensed current signal based on the sensed first current, and configured to sense a second current through the second switch and to generate a second sensed current signal based on the sensed second current. An output circuit is coupled to the current sensing circuit and is configured to generate a failure signal based on the first sensed current signal and the second sensed current signal.
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公开(公告)号：US11077755B2
公开(公告)日：2021-08-03
申请号：US16420875
申请日：2019-05-23
Applicant: STMicroelectronics S.r.l.
Inventor： Orazio Pennisi , Valerio Bendotti , Vanni Poletto
IPC: B60L3/00 , G01R31/385 , B60L50/64 , H02J7/00 , H03M3/00
Abstract: A circuit includes a differential stage configured to provide a differential output signal. An analog-to-digital converter is coupled to first and second output nodes of the differential stage. The analog-to-digital converter is configured to provide an output signal that is a function of the differential output signal from the differential stage. A multiplexer is configured to receive a differential input signal. The multiplexer includes a test switch switchable between a conductive state and a non-conductive state. In the conductive state, the test switch couples the first input node and the second input node of the differential stage. Test signal injection circuitry is activatable to force a differential current through the differential stage. The circuit is selectively switchable between an operational mode and a self-test mode.
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公开(公告)号：US10917087B2
公开(公告)日：2021-02-09
申请号：US16719053
申请日：2019-12-18
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G01R19/165 , G05B11/42 , G05F1/618 , G05F1/56 , H02J7/34
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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公开(公告)号：US20190267991A1
公开(公告)日：2019-08-29
申请号：US16274844
申请日：2019-02-13
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G05B11/42 , G01R19/165
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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公开(公告)号：US12241946B2
公开(公告)日：2025-03-04
申请号：US18335511
申请日：2023-06-15
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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