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公开(公告)号：US11894657B2
公开(公告)日：2024-02-06
申请号：US17360381
申请日：2021-06-28
Inventor： Romeo Letor , Vanni Poletto , Antoine Pavlin , Nadia Lecci , Alfio Russo
CPC classification number: H01S5/06216 , H01S5/0261 , H03K5/07
Abstract: An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.
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公开(公告)号：US12113444B2
公开(公告)日：2024-10-08
申请号：US17856657
申请日：2022-07-01
Inventor： Vanni Poletto , Antoine Pavlin
CPC classification number: H02M3/1586 , B60L53/22 , B60L58/20 , B60L2210/12 , B60L2210/14
Abstract: In an embodiment, a phase circuit includes: a bidirectional output stage configured to be coupled between a first battery and a second battery; a memory configured to store a number of active phases, and an identifier; and a synchronization circuit configured to receive a first clock signal and determine a start time of a switching cycle of the bidirectional output stage based on the number of active phases, the identifier, and the first clock signal, where the phase circuit is configured to control the timing of the switching of the bidirectional output stage based on the start time.
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公开(公告)号：US20240006998A1
公开(公告)日：2024-01-04
申请号：US17856657
申请日：2022-07-01
Inventor： Vanni Poletto , Antoine Pavlin
CPC classification number: H02M3/1586 , B60L53/22 , B60L58/20 , B60L2210/12 , B60L2210/14
Abstract: In an embodiment, a phase circuit includes: a bidirectional output stage configured to be coupled between a first battery and a second battery; a memory configured to store a number of active phases, and an identifier; and a synchronization circuit configured to receive a first clock signal and determine a start time of a switching cycle of the bidirectional output stage based on the number of active phases, the identifier, and the first clock signal, where the phase circuit is configured to control the timing of the switching of the bidirectional output stage based on the start time.
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公开(公告)号：US20220014187A1
公开(公告)日：2022-01-13
申请号：US17338157
申请日：2021-06-03
Inventor： Romeo Letor , Vanni Poletto , Antoine Pavlin , Alfio Russo , Nadia Lecci
IPC: H03K17/687 , H01S5/042
Abstract: In accordance with an embodiment, a pulse generator circuit includes: an LC resonant circuit coupled between a first node and a reference node; a first switch coupled between the first node and the reference node; a switching network comprising a second switch coupled between the first node and a respective drive node; and drive circuit having outputs coupled to the first switch and to the second switch of the switching network. The drive circuit configured to, in repeating cycles: close the first switch when a current flowing through an inductor of the LC resonant circuit increases during a resonant cycle, when the current flowing through the inductor reaches a threshold value, open the first switch, close the second switch of the switching network for a pulse duration time when the first switch is open, and open the second switch at an expiration of the pulse duration time.
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公开(公告)号：US20220013984A1
公开(公告)日：2022-01-13
申请号：US17360381
申请日：2021-06-28
Inventor： Romeo Letor , Vanni Poletto , Antoine Pavlin , Nadia Lecci , Alfio Russo
Abstract: An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20240204478A1
公开(公告)日：2024-06-20
申请号：US18533585
申请日：2023-12-08
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronis S.r.l.
Inventor： Romeo Letor , Alfio Russo , Nadia Lecci , Antonio Filippo Massimo Pizzardi , Antoine Pavlin , Vanni Poletto , Marco Brera , Simone Bianchi
IPC: H01S5/026 , G01S7/481 , H01S5/02326 , H01S5/40
CPC classification number: H01S5/0261 , G01S7/4814 , H01S5/02326 , H01S5/4025
Abstract: In a driver circuit couplable to laser diodes, a semiconductor body has a first surface. First and second control switches have drains coupled to a drain metallization, which is couplable to a power supply line, and sources coupled to respective first and second source metallizations, which are couplable to cathode terminals of the laser diodes and a reference node. A plurality of high-side switches have drains coupled to the drain metallization and sources coupled to third source metallizations, each of which is coupled to a respective drive output node for driving an anode terminal of a respective laser diode. The drain, first, second and third source metallizations face the first surface of the semiconductor body, which faces the laser diodes. The second and third source metallizations are aligned with one another and are superimposed to the respective source terminals of the second control switch and high-side switches.
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公开(公告)号：US11719761B2
公开(公告)日：2023-08-08
申请号：US17407747
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
CPC classification number: G01R31/64 , G01R27/2605 , G01R31/006
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号：US20230054951A1
公开(公告)日：2023-02-23
申请号：US17407725
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
IPC: G01R19/10 , H03M1/12 , H03M3/00 , B60R21/017
Abstract: A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.
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公开(公告)号：US11079442B2
公开(公告)日：2021-08-03
申请号：US16420992
申请日：2019-05-23
Applicant: STMicroelectronics S.r.l.
Inventor： Orazio Pennisi , Valerio Bendotti , Vanni Poletto , Vittorio D'Angelo
Abstract: A method of operating a control device includes performing an open load test or a current leakage test. The open load test includes activating a first current and then a second current and sensing with the first current and the second current activated, respectively, a first voltage drop and a second voltage drop between charge distribution pins and charge sensing pins of the control device. Respective differences are calculated between the first voltage drop and the second voltage drop sensed with the first current and the second current activated, respectively. These differences are compared with respective thresholds and an open circuit condition is declared as a result of the differences calculated reaching these thresholds.
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公开(公告)号：US10560092B2
公开(公告)日：2020-02-11
申请号：US16274844
申请日：2019-02-13
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G01R19/165 , G05B11/42
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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