Abstract:
The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method and apparatus for transmitting/receiving Channel State Information (CSI) is provided for use in a Full Dimensional Multiple Input Multiple Output (FD-MIMO) system. A channel state information (CSI) reception for a base station according to the present disclosure for use in a wireless communication system includes transmitting CSI process configuration information to a terminal, transmitting a CSI Reference Signal (CSI-RS) to the terminal based on the CSI process configuration information, and receiving the CSI generated based on CSI-RS measurement result from the terminal, wherein the CSI process configuration information is configured to measure channel states of horizontal and vertical antenna arrays, the CSI includes a joint Channel Quality Indicator (CQI), and the joint CQI is determined based on the CQIs for the horizontal and vertical antennas arrays.
Abstract:
A composite membrane includes: an organic layer having a plurality of through holes; and ion conductive inorganic particles disposed in the through holes, wherein a hydrophobic coating layer is disposed on a surface of the ion conductive inorganic particles.
Abstract:
A base station capable of communicating with a user equipment (UE) includes a transceiver configured to transmit Channel State Information-Reference Signal (CSI-RS) according to a CSI-RS configuration comprising a number of antenna ports, and downlink signals containing the CSI-RS configuration and a precoding-matrix-construction configuration for precoding matrix indicator (PMI) reporting on physical downlink shared channels (PDSCH), the precoding-matrix-construction configuration comprising a first and second sampling factors, O1 and O2, and a first and second numbers, N1 and N2, receive, from the UE, uplink signals containing a precoding matrix indicator (PMI) derived using the CSI-RS according to the precoding-matrix-construction configuration, a controller configured to convert the PMI to one of predetermined precoding matrices. Other embodiments including UEs and methods are disclosed.
Abstract:
A method and an apparatus for detecting inter-cell interference in a mobile communication system are provided. A base station receives a reference signal (RS) from a terminal, generate one or more interference candidate RSs, calculate a cross correlation of the one or more interference candidate RSs and the received RS, estimate at least one of a size of a Resource Block (RB) an offset of the RB, a group index (U), and a cyclic shift (CS) by using a preset number of interference candidate RSs in an order of the large cross correlation. The base station further removes an interference signal or performs a direct reduction by using at least one of the estimated RB size, the RB offset, the timing offset, and the group index (U). According to the present disclosure, it is beneficial to mitigate or cancel inter-cell interference problem on an uplink transmission without any assistance of neighbor base stations and/or adjacent cells in a wireless communication system.
Abstract:
A lithium air battery including a composite cathode including a porous material and a first solid electrolyte; a lithium metal anode; an oxygen blocking layer adjacent to the anode; and a cathode interlayer disposed between the cathode and the oxygen blocking layer, wherein the cathode interlayer includes a lithium ion conducting second solid electrolyte.
Abstract:
An apparatus and method is proved that transmits and receives Reference Signals (RSs) in a wireless communication system using Multiple-Input and Multiple-Output (MIMO). A system adapted to the method is provided. The method includes: determining the number of RS transmission to two or more antennas, respectively, as the number of antennas included in respective ports, wherein each port include one or more antennas; creating transmit patterns so that they cyclically differ from each other every the number of RS transmission to transmit the created transmit patterns the number of RS transmission times; and mapping the RSs to one or more antennas according to the created, respective patterns, and transmitting the RSs in order.
Abstract:
An electronic device includes at least one processor, a Universal Flash Storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including a plurality of downstream lanes for transmitting data and a plurality of upstream lanes for transmitting data and storage including a cache memory and a plurality of non-volatile memories. The at least one processor transmits a first control signal to instruct measuring a temperature of the storage and identifying of the measured temperature exceeding a threshold value to the UFS device controller, receives a status signal indicating that the measured temperature exceeds the threshold value from the UFS device controller, and based on the status signal, transmits, to the UFS device controller, a second control signal to instruct that deactivating at least some of the plurality of downstream lanes and upstream lanes, or deactivating the cache memory in the storage.
Abstract:
A photoresist-removing composition includes a polar organic solvent, an alkyl ammonium hydroxide, an aliphatic amine not including a hydroxy group, and a monovalent alcohol. To manufacture a semiconductor device, a photoresist pattern may be formed on a substrate, and the photoresist-removing composition may then be applied to the photoresist pattern. To manufacture a semiconductor package, a photoresist pattern including a plurality of via holes may be formed on a substrate. A plurality of conductive posts including a metal may be formed inside the plurality of via holes, and the photoresist pattern may be removed by applying a photoresist-removing composition of the inventive concept to the photoresist pattern. A semiconductor chip may be adhered to the substrate between the respective conductive posts.
Abstract:
A semiconductor package includes a base substrate, a first semiconductor chip mounted on the base substrate, and a second semiconductor chip mounted on the first semiconductor chip. The first semiconductor includes first conductive connection structures that have a first pitch interval in a first direction and a second pitch interval in a second direction, and the second semiconductor chip includes second conductive connection structures that have the first pitch interval in the first direction and the second pitch interval in the second direction. The first conductive connection structures include first power connection structures, first ground connection structures, and first dummy structures. The first ground connection structure or the first dummy structure is between two first power connection structures neighboring in the first direction and between two first power connection structures neighboring in the second direction among the first power connection structures.
Abstract:
A stack semiconductor package including a base chip, at least two semiconductor chips stacked on the base chip, and a sealing material sealing the at least two semiconductor chips on the base chip may be provided. The at least two semiconductor chips may include an uppermost semiconductor chip and at least one under the uppermost semiconductor chip, the first semiconductor chip includes through electrodes at a central portion thereof along a first direction, the through electrodes arranged along a second direction perpendicular to the first direction, upper dummy pads on outer portions of a back side of the first semiconductor chip, the outer portions being a non-active surface of the first semiconductor chip and being at both sides of the central portion in the first direction, and a dummy pattern connecting the upper dummy pads with each other on the back side.