公开(公告)号：US11348910B2

公开(公告)日：2022-05-31

申请号：US16863736

申请日：2020-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Kyunghwa Yun ,  Daeseok Byeon

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/04 ,  G11C16/08

Abstract: A non-volatile memory device includes a first semiconductor layer having a stair area and a cell area having a memory cell array formed therein, and a second semiconductor layer including a page buffer connected to the memory cell array. The first semiconductor layer includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

公开(公告)号：US11282851B2

公开(公告)日：2022-03-22

申请号：US16662073

申请日：2019-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Chanho Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Chiweon Yoon

IPC: H01L27/11573 ,  H01L23/522 ,  H01L27/1157 ,  H01L29/78 ,  H01L29/94 ,  H01L27/11582

Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

公开(公告)号：US11237983B2

公开(公告)日：2022-02-01

申请号：US16865580

申请日：2020-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Taehong Kwon ,  Chanho Kim ,  Taeyun Lee

IPC: G06F12/02 ,  G06F12/123 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G06F12/14

Abstract: A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

公开(公告)号：US11233042B2

公开(公告)日：2022-01-25

申请号：US16850493

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Joo-Yong Park ,  Daeseok Byeon

IPC: H01L25/18 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11582 ,  H01L49/02 ,  H01L27/11565 ,  H01L23/00 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device, including a first chip and a second chip stacked on the first chip may be provided. The first chip may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, and second contact plugs, and a passive device on and electrically connected to the second contact plugs. The second chip may include a second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip may further include gate electrodes, and cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes. The first passive device may be vertically between the gate electrodes and the second contact plugs and may include a first contact line.

公开(公告)号：US11120843B2

公开(公告)日：2021-09-14

申请号：US16816476

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L23/522 ,  G11C5/06 ,  G11C5/04 ,  G11C7/18

Abstract: A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.

公开(公告)号：US11087844B2

公开(公告)日：2021-08-10

申请号：US16944312

申请日：2020-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Kyunghwa Yun ,  Daeseok Byeon

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region. The memory cell region includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

公开(公告)号：US10381078B2

公开(公告)日：2019-08-13

申请号：US15992840

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dong-Kil Yun ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C14/00 ,  H01L27/11578 ,  H01L27/108 ,  H01L27/1157 ,  G11C11/4094 ,  G11C11/408 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/4091 ,  G11C16/04

Abstract: A semiconductor memory includes a first memory cell array in a first region of a substrate and a second memory cell array in a second region of the substrate. The first memory cell array includes cell strings, and each cell string includes non-volatile memory cells stacked in a direction perpendicular to the substrate. The second memory cell array includes volatile memory cells, and each volatile memory cell includes a select transistor and a capacitor. The capacitor includes at least one contact electrically connected with the select transistor and having a second height corresponding to a first height of each cell string, and at least one second contact supplied with a ground voltage, having a third height corresponding to the first height of each cell string, adjacent to the at least one first contact, and electrically disconnected with the at least one first contact.

公开(公告)号：US20190189632A1

公开(公告)日：2019-06-20

申请号：US16030170

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Yeol LEE ,  Chanho Kim

IPC: H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04

Abstract: A memory device includes a substrate, a first memory structure including a plurality of first word lines stacked on the substrate in a direction perpendicular to a top surface of the substrate, an inter-metal layer on the first memory structure and including a plurality of intermediate pads connected with separate, respective first word lines of the plurality of first word lines, a second memory structure including a plurality of second word lines stacked on the inter-metal layer in the direction perpendicular to the top surface of the substrate, and an upper metal layer on the second memory structure and including a plurality of upper pads connected with separate, respective second word lines of the plurality of second word lines.

公开(公告)号：US20250031376A1

公开(公告)日：2025-01-23

申请号：US18582722

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junil Lee ,  Yongjun Kim ,  Chanho Kim ,  Sangwan Nam ,  Ryoongbin Lee

IPC: H10B43/40 ,  G11C16/30 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device may include a first semiconductor structure including a substrate, an active region in the substrate, a device isolation region defining the active region, and a capacitor structure on the device isolation region and vertically overlapping the device isolation region. The capacitor structure may include a first electrode structure extending in a first direction and including first capacitor electrodes stacked in the first direction, a second electrode structure including second capacitor electrodes stacked in the first direction, and a first insulating structure between the first electrode structure and the second electrode structure. Each of the first capacitor electrodes and the second capacitor electrodes are alternately arranged and spaced apart from each other in a second direction parallel to an upper surface of the substrate, extend in a third direction perpendicular to the first direction and the second direction, and has a plate shape.

公开(公告)号：US20240334699A1

公开(公告)日：2024-10-03

申请号：US18424495

申请日：2024-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghak Son ,  Kyunghwa Yun ,  Chanho Kim

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: An example memory device includes a plurality of memory blocks, each including a cell region and a cell wiring region. At least one memory block includes a wordline pattern portion and a channel structure. The wordline pattern portion is provided in the cell region and the cell wiring region, and includes wordlines spaced apart from each other and stacked in a first direction. The channel structure is provided in the cell region to extend in the first direction. The wordline pattern portion extends a second direction, perpendicular to the first direction, when viewed from above, and has at least one staircase portion including a first staircase pattern, having sequentially descending staircases, and a second staircase pattern, having sequentially ascending staircases. The first staircase pattern and the second staircase pattern are provided in different numbers in the at least one memory block.