公开(公告)号：US11552033B2

公开(公告)日：2023-01-10

申请号：US17155657

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US11471802B2

公开(公告)日：2022-10-18

申请号：US16846963

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wan-Ku Kang ,  Jung-Geun Lee ,  Jongho Lee ,  Moohyung Lee ,  Yeonwoo Cho

IPC: B01D29/13 ,  B01D35/30

Abstract: A filter assembly includes a filter holder into which a part of the filter is insertable, and a lock mounted to the filter holder and configured to lock and release the filter to and from the filter holder. The lock includes a guide coupled to the filter holder and configured to be linearly movable to transmit a force in a direction into which the filter is inserted, a pusher configured to transmit a force in a direction opposite to the direction, into which the filter is inserted, by an elastic member, a stopper rotatably received in the pusher to be arranged between the pusher and the guide, and configured to linearly move the filter holder by being linearly moved by the guide and the pusher, and a cam configured to lock and release the filter to and from the filter holder by guiding rotation and linear movement of the stopper.

公开(公告)号：US11147519B2

公开(公告)日：2021-10-19

申请号：US16426225

申请日：2019-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Youngbeom Kim ,  Doohee Lee ,  Jongho Lee ,  Junki Lee ,  Sangyoung Zho

IPC: G01R31/01 ,  A61B5/00 ,  A61B5/055 ,  G01R33/56 ,  G01R33/50 ,  G06F30/20

Abstract: Imperfect RF pulses in a multi-spin-echo (MSE) sequence disturb prediction of relaxation times. Provided are a magnetic resonance imaging (MRI) apparatus and method of operating the same, whereby a characteristic parameter value may be acquired from MR signal data via training using an artificial neural network (ANN) and a parametric map may be generated based on the acquired characteristic parameter value. The ANN may be trained to compensate for imperfect RF pulses while providing reduced computation times to produce an output image.

公开(公告)号：US20210159213A1

公开(公告)日：2021-05-27

申请号：US17001978

申请日：2020-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewook Kim ,  Jongho Lee ,  Jeongjoon Oh ,  Hyeon Hwang

IPC: H01L25/065

Abstract: A semiconductor package includes a package substrate; a plurality of lower chip structures on the package substrate; an upper chip structure on the plurality of lower chip structures and covering portions of upper surfaces of the plurality of lower chip structures; a non-conductive adhesive layer on a lower surface of the upper chip structure and receiving upper portions of the plurality of lower chip structures; and a molded member on the plurality of lower chip structures and the upper chip structure.

公开(公告)号：US10991694B2

公开(公告)日：2021-04-27

申请号：US16137625

申请日：2018-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Jongho Lee ,  Geumjong Bae

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L29/417

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

公开(公告)号：US10598752B2

公开(公告)日：2020-03-24

申请号：US15807800

申请日：2017-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Jin-hee Jeong ,  Jongho Lee

IPC: G01V3/00 ,  G01R33/56 ,  G01R33/561 ,  G01R33/483

Abstract: Provided are a magnetic resonance imaging (MRI) apparatus and method for obtaining a plurality of MR images having different contrasts by using a single pulse sequence. The MRI apparatus includes a controller configured to control a pulse sequence of one cycle to be applied to a plurality of slices of an object, wherein the one cycle includes a first obtaining section during which a first inversion radio frequency (RF) pulse is applied to a first slice of the object and a second obtaining section during which a second inversion RF pulse is applied to a second slice of the object adjacent to the first slice, and to sequentially obtain a first MR signal for capturing a first MR image of the first slice, a second MR signal for capturing at least one second MR image of the second slice adjacent to the first slice, and a third MR signal for capturing at least one third MR image of the first slice, during the first obtaining section.

公开(公告)号：US20200027818A1

公开(公告)日：2020-01-23

申请号：US16285480

申请日：2019-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunki Kim ,  Sangsoo Kim ,  Seung Hwan Kim ,  Kyung Suk Oh ,  Yongkwan Lee ,  Jongho Lee

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00

Abstract: Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.

公开(公告)号：US10090328B2

公开(公告)日：2018-10-02

申请号：US15429719

申请日：2017-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil Yang ,  Dong Il Bae ,  Geumjong Bae ,  Seungmin Song ,  Jongho Lee

IPC: H01L23/48 ,  H01L27/12 ,  H01L27/02 ,  H01L29/78

Abstract: A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.

公开(公告)号：US12300668B2

公开(公告)日：2025-05-13

申请号：US17889053

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raehyung Do ,  Seunghyun Go ,  Jungsik Lee ,  Jongho Lee ,  Younghun Cheong ,  Cheolsoo Han

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package comprising a substrate including substrate pads on a top surface thereof, a first upper semiconductor chip on the substrate and including conductive chip pads, and bonding wires coupled to the substrate pads and the first upper semiconductor chip. The bonding wires include first and second bonding wires. The substrate has a first region between the conductive chip pads and the substrate pads, and a second region between the first region and the substrate pads. The second bonding wire has a maximum vertical level on the first region of the substrate. On the first region of the substrate, the first bonding wire is at a level higher than that of the second bonding wire. On the second region of the substrate, the second bonding wire is at a level higher than that of the first bonding wire.

公开(公告)号：US20250015026A1

公开(公告)日：2025-01-09

申请号：US18897635

申请日：2024-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.