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公开(公告)号：US20220140100A1
公开(公告)日：2022-05-05
申请号：US17405619
申请日：2021-08-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeonchoo CHO , Kyung-Eun BYUN , Hyeonjin SHIN
IPC: H01L29/45
Abstract: Disclosed is a semiconductor device including a surface-treated semiconductor layer. The semiconductor device includes a metal layer, a semiconductor layer electrically contacting the metal layer and having a surface treated with an element having an electron affinity of about 4 eV or greater, and a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure.
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公开(公告)号：US20220068704A1
公开(公告)日：2022-03-03
申请号：US17411467
申请日：2021-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keunwook SHIN , Sanghoon AHN , Woojin LEE , Kyung-Eun BYUN , Junghoo SHIN , Hyeonjin SHIN , Yunseong LEE
IPC: H01L21/768
Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.
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公开(公告)号：US20210159183A1
公开(公告)日：2021-05-27
申请号：US17165246
申请日：2021-02-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Eun BYUN , Keunwook SHIN , Yonghoon KIM , Hyeonjin SHIN , Hyunjae SONG , Changseok LEE , Changhyun KIM , Yeonchoo CHO
IPC: H01L23/532 , H01L21/768 , H01L23/522
Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.
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公开(公告)号：US20210074543A1
公开(公告)日：2021-03-11
申请号：US17012661
申请日：2020-09-04
Inventor： Changhyun KIM , Sangwoo KIM , Kyung-Eun BYUN , Hyeonjin SHIN , Ahrum SOHN , Jaehwan JUNG
Abstract: Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: depositing a transition metal dichalcogenide thin film on a substrate; and heat-treating the deposited transition metal dichalcogenide thin film.
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公开(公告)号：US20210043452A1
公开(公告)日：2021-02-11
申请号：US16851675
申请日：2020-04-17
Inventor： Changhyun KIM , Sang-Woo KIM , Kyung-Eun BYUN , Hyeonjin SHIN , Ahrum SOHN , Jaehwan JUNG
IPC: H01L21/02
Abstract: Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO2) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS2) substrate.
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Patent Agency Ranking
公开(公告)号：US20250126886A1
公开(公告)日：2025-04-17
申请号：US18917227
申请日：2024-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Eun BYUN , Minsu SEOL , Junyoung KWON , Huije RYU
IPC: H01L27/092 , H01L29/24 , H01L29/76 , H01L29/786
Abstract: Provided is a semiconductor device including a two-dimensional (2D) material. The semiconductor device may include a first channel including a first 2D material layer, a second channel apart from the first channel in a first direction and including a second 2D material layer, a common gate electrode between the first channel and the second channel, a first electrode and a second electrode apart from each other and respectively in contact with the first channel and the second channel, and a common electrode apart from the first electrode and the second electrode in a second direction intersecting the first direction and in contact with the first channel and the second channel. One of the first channel and the second channel may be an n-type channel and the other one may be a p-type channel.
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公开(公告)号：US20250126885A1
公开(公告)日：2025-04-17
申请号：US18913192
申请日：2024-10-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minsu SEOL , Kyung-Eun BYUN , Changhyun KIM , Eunkyu LEE
IPC: H01L27/092 , H01L21/762 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A semiconductor device includes a dielectric wall provided in a direction perpendicular to a substrate, a first metal oxide field effect transistor (MOSFET) provided on one side surface of the dielectric wall, a second MOSFET provided above the first MOSFET in a direction perpendicular to the substrate, and a third MOSFET provided in parallel with the first MOSFET on the other side surface of the dielectric wall.
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公开(公告)号：US20240234557A1
公开(公告)日：2024-07-11
申请号：US18515102
申请日：2023-11-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minsu SEOL , Jeeeun YANG , Sangwook KIM , Kyung-Eun BYUN , Eunkyu LEE
IPC: H01L29/76 , H01L21/02 , H01L29/24 , H01L29/423 , H01L29/66
CPC classification number: H01L29/7606 , H01L21/02568 , H01L29/24 , H01L29/4236 , H01L29/66969
Abstract: Disclosed are a semiconductor device, a method of manufacturing the same, and an electronic element and an electronic apparatus each including the semiconductor device. The semiconductor device may include a substrate, a channel layer on the substrate, a first electrode and a second electrode on two opposite ends of the channel layer, respectively, and spaced apart from each other, a gate electrode on the channel layer and spaced apart from the first electrode and the second electrode, a gate dielectric material provided between the channel layer and the gate electrode, and a chalcogen compound layer being at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer.
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公开(公告)号：US20240178144A1
公开(公告)日：2024-05-30
申请号：US18521994
申请日：2023-11-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keunwook SHIN , Hyeonjin SHIN , Sangwon KIM , Changhyun KIM , Baekwon PARK , Kyung-Eun BYUN
IPC: H01L23/532
CPC classification number: H01L23/53276 , H01L23/53295
Abstract: An interconnect structure may include a first dielectric layer including a trench, a first conductive layer in the trench and including a plurality of first graphene layers stacked in a direction from an inner surface of the trench toward a center of the trench, a second dielectric layer on the first dielectric layer and including a through hole extending to the trench, and a second conductive layer in the through hole.
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40.发明公开公开(公告)号：US20240170562A1
公开(公告)日：2024-05-23
申请号：US18366366
申请日：2023-08-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junyoung KWON , Minsu SEOL , Kyung-Eun BYUN , Changseok LEE , Minseok YOO
CPC classification number: H01L29/7606 , H01L29/24 , H01L29/66969
Abstract: A semiconductor device may include a first two-dimensional (2D) material layer, a second 2D material layer, a first electrode, a second electrode, a third electrode, a first gate electrode. and a second gate electrode. A Fermi-level may be pinned on an interfacial surface between the first 2D material layer and the first electrode. The Fermi-level may be depinned on an interfacial surface between the second 2D material layer and the first electrode.
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