公开(公告)号：US11605441B1

公开(公告)日：2023-03-14

申请号：US17461380

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kiheung Kim ,  Sungrae Kim ,  Junhyung Kim ,  Kijun Lee ,  Myungkyu Lee ,  Changyong Lee ,  Sanguhn Cha

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/12

Abstract: A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.

公开(公告)号：US20230004308A1

公开(公告)日：2023-01-05

申请号：US17704354

申请日：2022-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee

IPC: G06F3/06

Abstract: In a method of operating a memory controller, a decoding status flag is received from a memory module including a plurality of data chips and at least one parity chip. Each of the plurality of data chips and the at least one parity chip may include an on-die error correction code (ECC) engine. The decoding status flag is generated by the on-die ECC engines. A first number and a second number may be obtained based on the decoding status flag. The first number represents a number of first chips including an uncorrectable error that is uncorrectable by the on-die ECC engine. The second number represents a number of second chips including a correctable error that is correctable by the on-die ECC engine. At least one of a plurality of decoding schemes is selected based on at least one of the first number and the second number. A system ECC engine may perform ECC decoding on at least one of the first chips and the second chips based on the selected decoding scheme.

公开(公告)号：US11501823B2

公开(公告)日：2022-11-15

申请号：US16812850

申请日：2020-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangyun Kim ,  Younghun Seo ,  Hyejung Kwon ,  Myungkyu Lee ,  Sunghye Cho

IPC: G11C11/4091 ,  G11C11/56 ,  G11C11/4074 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.

公开(公告)号：US20210384919A1

公开(公告)日：2021-12-09

申请号：US17199803

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunae Lee ,  Kijun Lee ,  Yeonggeol Song ,  Myungkyu Lee ,  Seokha Hwang

IPC: H03M13/15 ,  G06F11/10

Abstract: An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.

公开(公告)号：US11068340B2

公开(公告)日：2021-07-20

申请号：US16792515

申请日：2020-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguhn Cha ,  Hoyoung Song ,  Myungkyu Lee ,  Sunghye Cho

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G11C11/408 ,  G06F12/0882 ,  G06F13/16 ,  G11C11/406 ,  G06F11/30

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

公开(公告)号：US20210194508A1

公开(公告)日：2021-06-24

申请号：US16987554

申请日：2020-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho ,  Chanki Kim ,  Yeonggeol Song

IPC: H03M13/15 ,  H03M13/11 ,  G06F11/10 ,  G06F9/30

Abstract: A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

公开(公告)号：US20210191810A1

公开(公告)日：2021-06-24

申请号：US16934677

申请日：2020-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghye Cho ,  Chanki Kim ,  Kijun Lee ,  Sanguhn Cha ,  Myungkyu Lee

IPC: G06F11/10 ,  H03M13/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array is coupled to word-line and bit-lines and is divided into sub array blocks. The error correction circuit generates parity data based on main data using an error correction code (ECC). The control logic circuit controls the error correction circuit and the I/O gating circuit based on a command and address. The control logic circuit stores the main data and the parity data in (k+1) target sub array blocks in the second direction among the sub array blocks, and controls the I/O gating circuit such that a portion of the (k+1) target sub array blocks store both of a portion of the main data and a portion of the parity data.

公开(公告)号：US10108494B2

公开(公告)日：2018-10-23

申请号：US15288227

申请日：2016-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunyeong Yu ,  Junjin Kong ,  Beom Kyu Shin ,  Myungkyu Lee ,  Jiyoup Kim ,  Dongmin Shin

IPC: G06F11/10 ,  G06F3/06

Abstract: A redundant array of inexpensive disks (RAID) controller of a RAID storage system that includes one or more storage devices includes an error correction code (ECC) result manager configured to manage information of ECC result indicators when a data chunk that includes one or more ECC data units having an uncorrectable ECC error is read from among a plurality of data chunks dispersively stored in the one or more storage devices, each of the plurality of data chunks including a plurality of ECC data units, the ECC result indicators respectively indicating whether the plurality of ECC data units included in the plurality of data chunks has an uncorrectable ECC error; and an uncorrectable error counter configured to calculate a number of ECC result indicators indicating an uncorrectable ECC error among ECC result indicators corresponding to ECC data units having a same order in each of the plurality of data chunks.

公开(公告)号：US09923580B2

公开(公告)日：2018-03-20

申请号：US14877448

申请日：2015-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun Lee ,  Myungkyu Lee ,  Sejin Lim ,  Junjin Kong

IPC: H03M13/37 ,  H03M13/15

CPC classification number: H03M13/3715 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/157

Abstract: The inventive concepts relate to an operation method of an error correction decoder correcting an error of data read from a nonvolatile memory. The operation method may include receiving the data from the nonvolatile memory, performing a first error correction with respect to the received data in a simplified mode, and performing, when the first error correction fails in the simplified mode, a second error correction with respect to the received data in a full mode. When the first error correction of the simplified mode is performed, a part of operations of the second error correction of the full mode may be omitted.

公开(公告)号：US12236996B2

公开(公告)日：2025-02-25

申请号：US18197084

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Ae Lee ,  Sunghye Cho ,  Kijun Lee ,  Kyomin Sohn ,  Myungkyu Lee

IPC: G11C11/406

Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.