公开(公告)号：US10332571B2

公开(公告)日：2019-06-25

申请号：US15951554

申请日：2018-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Ho Cha ,  Chankyung Kim ,  Sungchul Park ,  Hoyoung Song ,  Kwangchol Choe

IPC: G11C11/56 ,  G11C7/12 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.

公开(公告)号：US20170221546A1

公开(公告)日：2017-08-03

申请号：US15413907

申请日：2017-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoon Loh ,  Hoyoung Song ,  Sangwoong Shin

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time.

公开(公告)号：US11068340B2

公开(公告)日：2021-07-20

申请号：US16792515

申请日：2020-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguhn Cha ,  Hoyoung Song ,  Myungkyu Lee ,  Sunghye Cho

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G11C11/408 ,  G06F12/0882 ,  G06F13/16 ,  G11C11/406 ,  G06F11/30

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

公开(公告)号：US09165679B2

公开(公告)日：2015-10-20

申请号：US14030066

申请日：2013-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-min Oh ,  Yung-young Lee ,  Hoyoung Song ,  Chiwook Kim ,  Donghyun Sohn

IPC: G11C29/50 ,  G11C29/04 ,  G11C29/00 ,  G11C8/08 ,  G11C8/14

CPC classification number: G11C29/04 ,  G11C8/08 ,  G11C8/14 ,  G11C29/50 ,  G11C29/785 ,  G11C29/808

Abstract: Provided is a method of preventing simultaneous activation of redundancy memory line or spare word lines, the method including: programming a fail address of a memory line determined to be defective; reprogramming the fail address if a first spare line for the memory line is determined to be defective; storing additional information with respect to the reprogrammed fail address; and activating a second spare line and inactivating the first spare line, referring to the additional information.

Abstract translation: 提供了一种防止冗余存储器线或备用字线的同时激活的方法，所述方法包括：对确定为有缺陷的存储器线的故障地址进行编程; 如果存储线的第一备用线被确定为有缺陷，则重新编程故障地址; 存储关于重新编程的故障地址的附加信息; 并且参考附加信息激活第二备用线路并使第一备用线路停用。

公开(公告)号：US11656935B2

公开(公告)日：2023-05-23

申请号：US17351619

申请日：2021-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguhn Cha ,  Hoyoung Song ,  Myungkyu Lee ,  Sunghye Cho

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G11C11/408 ,  G06F12/0882 ,  G06F13/16 ,  G11C11/406 ,  G06F11/30

CPC classification number: G06F11/106 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1068 ,  G06F11/3037 ,  G06F12/0882 ,  G06F13/1673 ,  G11C11/4082 ,  G11C11/40615

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

公开(公告)号：US11615829B1

公开(公告)日：2023-03-28

申请号：US17244261

申请日：2021-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongha Kim ,  Hyunki Kim ,  Hoyoung Song

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device includes a memory cell array, a random bit generator, a comparator and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random bit generator generates a random binary code having a predetermined number of bits. The comparator compares the random binary code and a reference binary code to output a matching signal based on a result of the comparison. The refresh controller refreshes target memory cells from among the plurality of memory cells based on addresses accessed by a memory controller during a sampling period randomly determined based on the matching signal and a refresh command from the memory controller.

公开(公告)号：US20180233183A1

公开(公告)日：2018-08-16

申请号：US15951554

申请日：2018-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Ho Cha ,  Chankyung Kim ,  Sungchul Park ,  Hoyoung Song ,  Kwangchol Choe

IPC: G11C7/12 ,  G11C11/4094 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4099 ,  G11C7/06 ,  G11C7/14

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/065 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/565

Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.

公开(公告)号：US10658023B2

公开(公告)日：2020-05-19

申请号：US16379167

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoon Loh ,  Hoyoung Song ,  Sangwoong Shin

IPC: G11C7/00 ,  G11C11/406 ,  G06F3/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

Abstract: A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time.

公开(公告)号：US10297306B2

公开(公告)日：2019-05-21

申请号：US15900070

申请日：2018-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoon Loh ,  Hoyoung Song ,  Sangwoong Shin

IPC: G11C11/06 ,  G11C11/406 ,  G06F3/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

Abstract: A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time.

公开(公告)号：US09972371B2

公开(公告)日：2018-05-15

申请号：US15596558

申请日：2017-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Ho Cha ,  Chankyung Kim ,  Sungchul Park ,  Hoyoung Song ,  Kwangchol Choe

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/22 ,  G11C7/14

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/065 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.