公开(公告)号：US11726670B2

公开(公告)日：2023-08-15

申请号：US17704354

申请日：2022-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0673

Abstract: In a method of operating a memory controller, a decoding status flag is received from a memory module including a plurality of data chips and at least one parity chip. Each of the plurality of data chips and the at least one parity chip may include an on-die error correction code (ECC) engine. The decoding status flag is generated by the on-die ECC engines. A first number and a second number may be obtained based on the decoding status flag. The first number represents a number of first chips including an uncorrectable error that is uncorrectable by the on-die ECC engine. The second number represents a number of second chips including a correctable error that is correctable by the on-die ECC engine. At least one of a plurality of decoding schemes is selected based on at least one of the first number and the second number. A system ECC engine may perform ECC decoding on at least one of the first chips and the second chips based on the selected decoding scheme.

公开(公告)号：US20220374309A1

公开(公告)日：2022-11-24

申请号：US17580048

申请日：2022-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

IPC: G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first coedword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

公开(公告)号：US11463110B2

公开(公告)日：2022-10-04

申请号：US16987554

申请日：2020-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho ,  Chanki Kim ,  Yeonggeol Song

IPC: H03M13/00 ,  H03M13/15 ,  G06F9/30 ,  G06F11/10 ,  H03M13/11

Abstract: A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

公开(公告)号：US11462292B1

公开(公告)日：2022-10-04

申请号：US17227582

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung Kim ,  Sanguhn Cha ,  Sungrae Kim ,  Sunghye Cho

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  H03M13/11 ,  H03M13/15 ,  G11C29/12

Abstract: An error correction circuit includes ECC encoder and an ECC decoder. The ECC encoder generates, based on a first main data obtained by selectively shifting data bits of a main data based on a LSB of a row address, a parity data using an ECC and stores a codeword including the main data and the parity data in a target page. The ECC decoder generates a syndrome based on a second main data obtained by selectively shifting data bits of the main data based on the LSB of the row address, the parity data and a parity check matrix based on the ECC, and corrects a single bit error or corrects two bit errors when the two bit errors occur in adjacent two memory cells based on the syndrome. The mis-corrected bit is generated when the multiple error bits are present in the main data.

公开(公告)号：US11437115B2

公开(公告)日：2022-09-06

申请号：US17326416

申请日：2021-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Hoyoun Kim ,  Suhun Lim ,  Sunghye Cho

IPC: G11C29/00 ,  G11C29/42 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.