-
公开(公告)号：US10410672B1
公开(公告)日：2019-09-10
申请号：US16104933
申请日：2018-08-19
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Zheng Wu
Abstract: Systems and methods are disclosed for applying multi-stage multiple input single output (MISO) circuits for fast adaptation. An apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, a MISO circuit. The MISO circuit may include a first stage filter having a first number of taps and configured to filter signal samples received from the first reader and the second reader and produce first filtered samples. The MISO circuit may also include a second stage filter having a second number of taps greater than the first number, and be configured to receive the first filtered samples corresponding to the first reader and the second reader from the first filter stage, filter the first filtered samples to produce second filtered samples, and combine the second filtered samples to produce a combined sample output.
-
公开(公告)号：US10298240B1
公开(公告)日：2019-05-21
申请号：US15950766
申请日：2018-04-11
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Kenneth John Evans , Jason Vincent Bellorado
Abstract: In certain embodiments, an apparatus may comprise a circuit configured to scale a phase control value from an external phase control resolution of an external clock frequency to an internal phase control resolution of an internal clock frequency to generate a target phase control value. The circuit may also determine a difference between a current phase control value and the target phase control value and determine a phase step value based on the difference. Further, the circuit may modify a current phase control value based on the phase step value and generate a phase controlled clock signal at the internal clock frequency using the modified phase control value. Additionally, the circuit may divide the phase controlled clock signal at the internal clock frequency to generate a phase controlled clock signal at the external clock frequency.
-
公开(公告)号：US10297281B1
公开(公告)日：2019-05-21
申请号：US15829426
申请日：2017-12-01
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow
IPC: G11B5/596 , G11B19/20 , G11B15/087
Abstract: Systems and methods are disclosed for detection of a servo sector on a data storage medium. A circuit may be configured to sample a signal, and determine preamble sample values from the sample values that correspond to a preamble pattern. When a preamble is detected, the circuit may continue to perform preamble detection, as well as determine signal reading parameters to apply during a servo timing mark (STM) search state based on the preamble sample values. In response to locating the STM, the circuit may generate an indication that the STM is located. In response to not locating the STM, the circuit may extend an STM search timeout period when the preamble pattern is still detected, or increment an STM search counter when the preamble pattern is not detected. The circuit may exit the STM search state when the STM search counter exceeds the STM search timeout period.
-
公开(公告)号：US10276197B2
公开(公告)日：2019-04-30
申请号：US15793864
申请日：2017-10-25
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow
Abstract: An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.
-
公开(公告)号：US20180367164A1
公开(公告)日：2018-12-20
申请号：US15793870
申请日：2017-10-25
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Vincent Brendan Ashe , Rishi Ahuja
IPC: H03M13/41 , H03M1/00 , H04B1/7105 , H03M13/29
Abstract: An apparatus may include a circuit configured to process an input signal using a set of channel parameters. The circuit may produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit may further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit may perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.
-
Patent Agency Ranking
公开(公告)号：US20180366156A1
公开(公告)日：2018-12-20
申请号：US15722641
申请日：2017-10-02
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Zheng Wu
IPC: G11B20/10
Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.
-
公开(公告)号：US10084553B1
公开(公告)日：2018-09-25
申请号：US15389385
申请日：2016-12-22
Applicant: Seagate Technology LLC
Inventor： Jason Vincent Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: H04L7/0332 , H04L1/00 , H04L7/0029 , H04L25/03057 , H04L25/03286 , H04L25/03318
Abstract: In certain embodiments, a method may include receiving one or more equalized samples of an input signal. The method may further include mitigating one or more excursions in the one or more equalized samples based on one or more current decisions of an iterative decoding process to generate compensated equalized samples. In addition, the method may include performing iterative decoding operations based on the compensated equalized samples, updating the current decisions of the iterative decoding process and outputting the current decisions as a converged result when the iterative decoding operations have converged for the compensated equalized samples.
-
公开(公告)号：US09928854B1
公开(公告)日：2018-03-27
申请号：US15586217
申请日：2017-05-03
Applicant: Seagate Technology LLC
Inventor： Jason Charles Jury , Marcus Marrow , Michael J Link , Jason Bellorado
CPC classification number: G11B5/012 , G06F11/0793 , G11B5/035 , G11B5/09 , G11B21/106 , G11B2005/0013
Abstract: An apparatus may include a circuit configured to generate a set of first ADC samples based on a first signal associated with a first read head position and a failed segment and to generate a set of second ADC samples based on a second signal associated with a second read head position and the failed segment. The circuit may then generate, by a MISO equalizer, a set of equalized ADC samples based on the set of first ADC samples and the set of second ADC samples.
-
公开(公告)号：US11735214B2
公开(公告)日：2023-08-22
申请号：US17890580
申请日：2022-08-18
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: G11B5/59616 , G11B5/012
Abstract: Systems and methods are disclosed for synchronous writing of a grain patterned medium. The systems and methods can be implemented within a data storage device having a grain patterned medium. Further, a calibration process to determine a count of bits between servo wedges can be implemented in manufacturing, within the data storage device, or both. In some examples, the data storage device, during operation, can utilize the count of bits to perform synchronous writing, determine write errors, or both. Further, the servo wedge of the grain patterned medium may be patterned with a same or similar grain pattern as the data area that follows the servo wedge. Such a data storage device can implement a single clock for reading a servo wedge and writing a data area.
-
公开(公告)号：US11475912B1
公开(公告)日：2022-10-18
申请号：US17345759
申请日：2021-06-11
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: Systems and methods are disclosed for synchronous writing of a grain patterned medium. The systems and methods can be implemented within a data storage device having a grain patterned medium. Further, a calibration process to determine a count of bits between servo wedges can be implemented in manufacturing, within the data storage device, or both. In some examples, the data storage device, during operation, can utilize the count of bits to perform synchronous writing, determine write errors, or both. Further, the servo wedge of the grain patterned medium may be patterned with a same or similar grain pattern as the data area that follows the servo wedge. Such a data storage device can implement a single clock for reading a servo wedge and writing a data area.
-
-
-
-
-
-
-
-
-
Search Results
66
records
(took 0.021 seconds)
