公开(公告)号：US20180349301A1

公开(公告)日：2018-12-06

申请号：US15610815

申请日：2017-06-01

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa

IPC: G06F13/16 ,  G06F13/40 ,  G11C16/10 ,  G11C16/26

Abstract: Method and apparatus for managing a non-volatile memory (NVM). In some embodiments, a memory module has a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A controller is adapted to communicate commands and data to the MME circuit via an intervening data bus. The controller operates to reset the MME circuit by issuing a reset command to the MME circuit over the data bus, activating a decoupling circuit coupled between the data bus and a reference line at a reference voltage level to remove capacitance from the data bus resulting from the reset command, and subsequently sensing a voltage on the data bus. In some cases, multiple MME circuits and NVMs may be arranged on a plurality of flash dies which are concurrently reset by the controller.

公开(公告)号：US20180349266A1

公开(公告)日：2018-12-06

申请号：US15609198

申请日：2017-05-31

Applicant: Seagate Technology, LLC

Inventor： Timothy Canepa ,  Ryan J. Goss ,  Stephen Hanna

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0688 ,  G06F2212/7201

Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.

公开(公告)号：US20180024942A1

公开(公告)日：2018-01-25

申请号：US15217863

申请日：2016-07-22

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Timothy Canepa ,  Ramdas Kachare

IPC: G06F12/14 ,  H04L9/08

CPC classification number: H04L9/088 ,  H04L9/0897 ,  H04L9/3228

Abstract: Systems and methods for using encryption keys to manage data retention are described. In one embodiment, the systems and methods may include receiving data such as user data from a host of the storage drive, encrypting the data using an encryption key, writing the encrypted data to the storage drive, and retaining the encrypted data on the storage drive based at least in part on a validity of the encryption key.

公开(公告)号：US11449431B2

公开(公告)日：2022-09-20

申请号：US15608127

申请日：2017-05-30

Applicant: Seagate Technology LLC

Inventor： Mark Ish ,  Timothy Canepa ,  David S. Ebsen

IPC: G06F12/0888 ,  G06F12/02 ,  G06F9/4401

Abstract: A data storage device may consist of a non-volatile memory having rewritable in-place memory cells each with a read-write asymmetry. The non-volatile memory can store boot data that is subsequently loaded by a selection module of the data storage device. The selection module may bypass a memory buffer of the data storage device to load the boot data.

公开(公告)号：US10754555B2

公开(公告)日：2020-08-25

申请号：US16201733

申请日：2018-11-27

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Jeffrey Munsil ,  Jackson Ellis ,  Mark Ish

IPC: G06F12/02 ,  G06F3/06

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

公开(公告)号：US10303598B2

公开(公告)日：2019-05-28

申请号：US15196363

申请日：2016-06-29

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Leonid Baryudin ,  Stephen D. Hanna ,  Alex G. Tang

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/10

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller generally includes a processor, a cache and a hardware assist circuit. The processor may be configured to initiate a recycle operation by generation of a start index. The cache may be configured to buffer a first level of a map and less than all of a second level of the map. The hardware assist circuit may be configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.

公开(公告)号：US10284231B2

公开(公告)日：2019-05-07

申请号：US15610744

申请日：2017-06-01

Applicant: Seagate Technology, LLC

Inventor： Timothy Canepa

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/35 ,  G06F3/06 ,  G06F12/02 ,  G11C29/52 ,  G11C29/02 ,  G11C29/42 ,  H03M13/11 ,  H03M13/15

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a solid-state non-volatile memory (NVM) has a total user data storage capacity and an overprovisioning (OP) level. A control circuit writes parity data sets to the NVM each having a plurality of code words and an outer code. The code words include inner codes at an inner code rate to detect and correct read errors in a user data payload. The outer code includes parity data at an outer code rate to detect and correct read errors in the code words. A code adjustment circuit increases the inner code rate to compensate for a measured parameter associated with the NVM, and decreases the outer code rate to maintain the data capacity and OP levels above selected thresholds.

公开(公告)号：US10248330B2

公开(公告)日：2019-04-02

申请号：US15608203

申请日：2017-05-30

Applicant: Seagate Technology LLC

Inventor： Jackson Ellis ,  Jeffrey Munsil ,  Timothy Canepa ,  Stephen Hanna

IPC: G06F12/00 ,  G06F3/06

Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.

公开(公告)号：US20190095099A1

公开(公告)日：2019-03-28

申请号：US16201767

申请日：2018-11-27

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Stephen Hanna

IPC: G06F3/06 ,  G06F12/02

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.

公开(公告)号：US10229000B2

公开(公告)日：2019-03-12

申请号：US15232058

申请日：2016-08-09

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Stephen Hanna

IPC: G06F11/10 ,  H03M13/15 ,  G11C16/22 ,  G11C29/52 ,  G11C11/56 ,  G11C16/14 ,  H03M13/11

Abstract: Methods and structure for preventing lower page corruption in flash memory. One embodiment is a flash storage device that includes Multi-Level Cell (MLC) flash memory, Single-Level Cell (SLC) flash memory, and a controller coupled to the MLC flash memory and the SLC flash memory. The controller is configured to program host data to a lower page of the MLC flash memory, to generate an erasure code for the host data, and to store the erasure code in the SLC flash memory. The controller is also configured to detect an interrupted write operation to an upper page linked to the lower page, to retrieve the erasure code from the SLC flash memory, and to correct the host data of the lower page of the MLC flash memory using the erasure code.