公开(公告)号：US06544854B1

公开(公告)日：2003-04-08

申请号：US09724444

申请日：2000-11-28

申请人： Helmut Puchner ,  Gary K. Giust

发明人： Helmut Puchner ,  Gary K. Giust

IPC分类号： H01L21336

CPC分类号： H01L29/66651 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7833 ,  Y10S438/933

摘要： A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon germanium channel layer on the substrate. A gate insulation layer is formed on top of the strained silicon germanium channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source-drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal. Thus, standard materials for the spacer, such as silicon oxide or silicon nitride are not preferred for this application, because they tend to be transparent to the laser beam emissions.

公开(公告)号：US06504219B1

公开(公告)日：2003-01-07

申请号：US09960765

申请日：2001-09-21

申请人： Helmut Puchner ,  Shih-Fen Huang

发明人： Helmut Puchner ,  Shih-Fen Huang

IPC分类号： H01L27095

CPC分类号： H01L21/8238 ,  H01L21/76237

摘要： Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.

摘要翻译： 提供了一种用于在STI沟槽底部形成铟场注入的技术，以加强场氧化物下的p阱，但不会削弱场氧化物下的n阱。 铟的扩散系数比硼的扩散系数小一个数量级，铟的激活电位足够高以使阱掺杂。 因此，即使在硼耗尽的情况下，注入的铟能够在场隔离下保持p-n阱结的p型掺杂浓度，并且氧化物/硅界面也能保持高浓度，从而避免穿透。

公开(公告)号：US06486064B1

公开(公告)日：2002-11-26

申请号：US09670448

申请日：2000-09-26

申请人： Helmut Puchner

发明人： Helmut Puchner

IPC分类号： H01L21302

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28247 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/3211 ,  Y10S438/914 ,  Y10S438/957

摘要： A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer. The impregnation is accomplished using a process that does not impregnate a significant amount of the first species in the exposed vertical faces of the gate electrode. The impregnated sacrificial layer, the exposed vertical faces of the gate electrode, and the impregnated exposed portions of the gate dielectric layer are exposed to an oxidizing environment, causing oxide growth on at least the exposed vertical faces of the gate electrode, and thereby covering the vertical faces of the gate electrode with oxide sidewalls. However, the oxidizing environment does not cause significant oxide growth under the impregnated sacrificial layer and the impregnated exposed portions of the gate dielectric layer. A second species is impregnated through the impregnated exposed portions of the gate dielectric layer into portions of the semiconductor substrate that underlie the impregnated exposed portions of the gate dielectric layer. The impregnated second species forms junctions in the portions of the semiconductor substrate that underlie the impregnated exposed portions of the gate dielectric layer.

公开(公告)号：US08283727B1

公开(公告)日：2012-10-09

申请号：US12636596

申请日：2009-12-11

申请人： Andrew Walker ,  Helmut Puchner ,  Sai Dhanraj ,  Kevin Jang

发明人： Andrew Walker ,  Helmut Puchner ,  Sai Dhanraj ,  Kevin Jang

IPC分类号： H01L23/62

CPC分类号： H01L29/7436 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0886 ,  H01L29/1016 ,  H01L29/41758 ,  H01L29/42308 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.

摘要翻译： 描述了具有静电放电保护的电路。 在一种情况下，电路包括被配置为在静电放电事件期间保护连接到电路节点的部件的触发装置，触发装置包括插入在栅氧化层和延伸漏极区之间的隔离结构。 靠近隔离结构的延伸漏极区域的一部分基本上是无金属的。

公开(公告)号：US08063655B2

公开(公告)日：2011-11-22

申请号：US11483686

申请日：2006-07-10

申请人： Helmut Puchner ,  Oliver Pohland

发明人： Helmut Puchner ,  Oliver Pohland

IPC分类号： G01R31/02

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/5002

摘要： A regulated circuit having a number of metal-oxide-semiconductor field effect transistors (MOS FETs) and a method for using the same are provided to reduce Negative Bias Temperature Instability degradation of the MOS FETs on the circuit. In one embodiment, the method involves steps of: (i) detecting degradation in performance of at least one of the MOS FETs causing a shift in threshold voltage (VT) of the MOS FET; and (ii) if the shift in VT exceeds a predetermined value, forward biasing the MOS FETs, thereby reducing or reversing the shift in VT. Optionally, the method includes an initial step of determining if the circuit is in a non-dynamic operating mode before forward biasing the MOS FETs. Other embodiments are also disclosed.

摘要翻译： 提供具有多个金属氧化物半导体场效应晶体管（MOS FET）的调节电路及其使用方法，以减少电路上的MOS FET的负偏压温度不稳定性劣化。 在一个实施例中，该方法包括以下步骤：（i）检测导致MOS FET的阈值电压（VT）偏移的至少一个MOS FET的性能下降; 和（ii）如果VT的偏移超过预定值，则向MOS偏置，从而减小或反转VT的偏移。 可选地，该方法包括在向前偏置MOS FET之前确定电路是否处于非动态操作模式的初始步骤。 还公开了其他实施例。

公开(公告)号：US07859899B1

公开(公告)日：2010-12-28

申请号：US12079802

申请日：2008-03-28

申请人： Kaveh Shakeri ,  Kavin Jaejune Jang ,  Helmut Puchner

发明人： Kaveh Shakeri ,  Kavin Jaejune Jang ,  Helmut Puchner

IPC分类号： G11C14/00

CPC分类号： G11C5/141 ,  G11C11/417

摘要： Non-volatile (NV) semiconductor memories and methods of operating the same to reduce or eliminate a need for an external capacitance are provided. In one embodiment, the memory includes a memory cell comprising a random access memory (RAM) portion and a NV memory portion, and the method comprises steps of: (i) initially erasing the NV memory portion; and (ii) on detecting a drop in power supplied to the memory, programming the NV memory portion with data from the RAM portion while powering the memory from a capacitor. On restoration of power data is recalled from the NV memory portion into the RAM portion, and the NV memory portion erased. Preferably, the capacitor is integrally formed on a single substrate with the NV memory portion and RAM portion. More preferably, the capacitor comprises intrinsic capacitance between elements of the memory formed on the substrate. Other embodiments are also disclosed.

摘要翻译： 提供了非易失性（NV）半导体存储器及其操作方法以减少或消除对外部电容的需要。 在一个实施例中，存储器包括存储单元，其包括随机存取存储器（RAM）部分和NV存储器部分，并且所述方法包括以下步骤：（i）最初擦除NV存储器部分; 以及（ii）在检测到提供给存储器的功率下降时，在从存储器供电的同时，从RAM部分的数据对NV存储器部分进行编程。 在从NV存储器部分恢复到RAM部分的电力数据的恢复中，NV存储器部分被擦除。 优选地，电容器与NV存储器部分和RAM部分一体地形成在单个基板上。 更优选地，电容器包括在衬底上形成的存储器的元件之间的固有电容。 还公开了其他实施例。

公开(公告)号：US07838937B1

公开(公告)日：2010-11-23

申请号：US11234255

申请日：2005-09-23

申请人： Andrew J. Walker ,  Helmut Puchner ,  Harold M. Kutz ,  James H. Shutt

发明人： Andrew J. Walker ,  Helmut Puchner ,  Harold M. Kutz ,  James H. Shutt

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L27/0262 ,  H01L29/87

摘要： Circuits including a laterally diffused output driver transistor and a distinct device configured to provide electrostatic discharge (ESD) protection for the laterally diffused output driver transistor are presented. In general, the device configured to provide ESD protection includes a drain extended metal oxide semiconductor transistor (DEMOS) transistor configured to breakdown at a lower voltage than a breakdown voltage of the laterally diffused output driver transistor. The laterally diffused output driver transistor may be a pull-down or a pull-up output driver transistor. The device also includes a silicon controlled rectifier (SCR) configured to inject charge within a semiconductor layer of the circuit upon breakdown of the DEMOS transistor. Moreover, the device includes a region configured to collect the charge injected from the SCR and further includes an ohmic contact region configured to at least partially affect the holding voltage of the SCR.

摘要翻译： 提供了包括横向扩散的输出驱动晶体管和被配置为为横向扩散输出驱动晶体管提供静电放电（ESD））保护的不同器件的电路。 通常，被配置为提供ESD保护的器件包括漏极延伸的金属氧化物半导体晶体管（DEMOS）晶体管，被配置为在比横向扩散的输出驱动晶体管的击穿电压低的电压下击穿。 横向扩散的输出驱动晶体管可以是下拉或上拉输出驱动晶体管。 该器件还包括被配置为在DEMOS晶体管击穿时在电路的半导体层内注入电荷的可控硅整流器（SCR）。 此外，该器件包括被配置为收集从SCR注入的电荷的区域，并且还包括被配置为至少部分地影响SCR的保持电压的欧姆接触区域。

公开(公告)号：US07768068B1

公开(公告)日：2010-08-03

申请号：US11758451

申请日：2007-06-05

申请人： Kevin Jang ,  Bill Phan ,  Helmut Puchner

发明人： Kevin Jang ,  Bill Phan ,  Helmut Puchner

IPC分类号： H01L29/735

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor topography and a method for forming a drain extended metal oxide semiconductor (DEMOS) transistor is provided. The semiconductor topography includes at least a portion of an extended drain contact region formed within a well region and a plurality of dielectrically spaced extension regions interposed between the well region and a channel region underlying a gate structure of the topography. The channel region of a first conductivity type and the well region of a second conductivity type opposite of the first conductivity type. In addition, the plurality of dielectrically spaced extension regions and the extended drain contact region are of the second conductivity type. Each of the plurality of dielectrically spaced extension regions has a lower net concentration of electrically active impurities than the well region. Moreover, the extended drain contact region has a greater net concentration of electrically active impurities than the well region.

摘要翻译： 提供半导体形貌和形成漏极延伸金属氧化物半导体（DEMOS）晶体管的方法。 半导体形貌包括形成在阱区内的扩展漏极接触区域的至少一部分和介于阱区域和位于形貌的栅极结构之下的沟道区域之间的多个介电间隔的延伸区域。 第一导电类型的沟道区和与第一导电类型相反的第二导电类型的阱区。 此外，多个介电间隔的延伸区域和延伸的漏极接触区域是第二导电类型。 多个介电间隔延伸区域中的每一个具有比阱区域更低的电活性杂质的净浓度。 此外，延伸的漏极接触区域具有比阱区域更大的电活性杂质的净浓度。

公开(公告)号：US07105413B2

公开(公告)日：2006-09-12

申请号：US11069501

申请日：2005-03-01

申请人： Jeong-Yeop Nahm ,  Helmut Puchner ,  Oliver Pohland ,  Yangzhong Xu

发明人： Jeong-Yeop Nahm ,  Helmut Puchner ,  Oliver Pohland ,  Yangzhong Xu

IPC分类号： H01L21/336

CPC分类号： H01L29/1045 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Methods for fabricating diffusion regions having steep concentration profiles within MOS devices while minimizing junction capacitance degradation are provided. In particular, methods are provided which include patterning a gate structure upon a semiconductor substrate and subsequently etching a recess in exposed portions of the substrate. In some cases, the method includes forming a first dopant region within the exposed portions prior to etching the recess. The method may additionally or alternatively include implanting a second set of dopants into portions of the semiconductor substrate bordering the recess. In either case, the method includes growing an epitaxial layer within the recess and implanting a third set of dopants into the semiconductor topography to form a second dopant region extending to a depth at least within the epitaxial layer. A resulting semiconductor topography includes a source/drain region comprising an upper portion consisting essentially of first dopants of a first conductivity type.

摘要翻译： 提供了在MOS器件内制造具有陡峭浓度分布的扩散区，同时最小化结电容劣化的方法。 特别地，提供了包括在半导体衬底上图案化栅极结构并随后蚀刻衬底的暴露部分中的凹部的方法。 在一些情况下，该方法包括在蚀刻凹槽之前在暴露部分内形成第一掺杂区域。 该方法可以附加地或替代地包括将第二组掺杂剂注入到与凹部接合的半导体衬底的部分中。 在任一情况下，该方法包括在凹槽内生长外延层并将第三组掺杂剂注入到半导体形貌中以形成延伸至至少在外延层内的深度的第二掺杂区。 得到的半导体形貌包括源/漏区，其包括基本上由第一导电类型的第一掺杂剂组成的上部。

公开(公告)号：US06734081B1

公开(公告)日：2004-05-11

申请号：US09999848

申请日：2001-10-24

申请人： Helmut Puchner ,  Venkatesh P. Gopinath

发明人： Helmut Puchner ,  Venkatesh P. Gopinath

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/268 ,  H01L21/823878

摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. A trench is etched in the integrated circuit substrate. A light barrier layer is then formed in the trench such that the light barrier layer at least partially fills the trench to create an isolation structure, the light barrier layer being adapted for absorbing laser light applied during laser thermal processing, thereby preventing damage to the integrated circuit substrate. For instance, the light barrier layer may be a conductive layer such as polysilicon. A dielectric layer is then formed over the isolation structure. The dielectric layer may be adapted for transferring heat generated by the laser thermal processing to the light barrier layer. For instance, the dielectric layer may be formed through oxidation of a top surface of the light barrier layer.

摘要翻译： 提供了用于在集成电路基板上形成隔离结构的方法和组合物。 在集成电路基板中蚀刻沟槽。 然后在沟槽中形成光阻挡层，使得光阻层至少部分地填充沟槽以产生隔离结构，光阻层适于吸收在激光热处理期间施加的激光，从而防止对集成 电路基板。 例如，光阻挡层可以是诸如多晶硅的导电层。 然后在隔离结构上形成介电层。 电介质层可以适于将由激光热处理产生的热量传递到光阻挡层。 例如，可以通过氧化遮光层的顶表面来形成电介质层。