公开(公告)号：US06616857B2

公开(公告)日：2003-09-09

申请号：US09942203

申请日：2001-08-29

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01B108

CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  Y10S438/933 ,  Y10T428/12674 ,  Y10T428/12701 ,  Y10T428/12875

摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7 A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

摘要翻译： 铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。 对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。 这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。 泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。 介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

公开(公告)号：US06440752B1

公开(公告)日：2002-08-27

申请号：US09817712

申请日：2001-03-26

申请人： Fengyan Zhang ,  Tingkai Li ,  Hong Ying ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Tingkai Li ,  Hong Ying ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01G706

CPC分类号： H01L28/75 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/55

摘要： An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.

摘要翻译： 用于铁电体器件的电极包括底部电极; 铁电层; 以及形成在强电介质层上并由金属组合形成的顶部电极，其包括从由铂和铱组成的金属组中的第一金属取得的金属和从由铝和钛组成的金属组中的第二金属; 其中所述顶部电极用作钝化层，并且其中所述顶部电极在氢气氛中的高温退火之后保持导电。 在铁电体器件中形成耐氢电极的方法包括形成底电极; 在底部电极上形成铁电层; 在铁电层上沉积顶部电极; 包括同时从由铂和铱组成的金属组中取出的第一金属; 和从由铝和钛组成的金属组中获取的第二金属; 以及通过在氧气氛中对所述结构退火以在所述顶部电极上形成氧化物钝化层来形成钝化层。

公开(公告)号：US06410343B1

公开(公告)日：2002-06-25

申请号：US09301420

申请日：1999-04-28

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  Y10S438/933 ,  Y10T428/12674 ,  Y10T428/12701 ,  Y10T428/12875

摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

摘要翻译： 铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。 对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。 这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。 泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。 介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

公开(公告)号：US07379320B2

公开(公告)日：2008-05-27

申请号：US11262117

申请日：2005-10-28

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L21/8247

CPC分类号： H01L27/1159 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585

摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

摘要翻译： 一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及 沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。 还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

公开(公告)号：US06819583B2

公开(公告)日：2004-11-16

申请号：US10345726

申请日：2003-01-15

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: a FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column.

摘要翻译： 铁基薄膜电阻存储阵列形成在基板上，并且包括以行和列为阵列排列的多个存储单元; 其中每个存储器单元包括：具有一对端子的FE电阻器和与每个电阻器相关联的晶体管，其中每个晶体管具有栅极，漏极和源极，并且其中每个晶体管的漏极电连接到 其相关电阻器; 连接到每个晶体管的栅极的字线; 连接到列中的每个存储单元的编程线; 以及连接到列中每个存储单元的位线。

公开(公告)号：US06759250B2

公开(公告)日：2004-07-06

申请号：US10196503

申请日：2002-07-15

申请人： Fengyan Zhang ,  Tingkai Li ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L28/56 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/75

摘要： The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD c-axis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties. A method of forming the above-mentioned multi-layered electrode ferroelectric structure is also provided.

摘要翻译： 提供了包括与锗酸铅（Pb5Ge3O11）薄膜结合使用的Pt / Ir层叠电极的铁电体结构。 该电极对基材表现出良好的粘合性，并且对氧和铅具有阻挡性能。 在MOCVD锗酸铅（Pb5Ge3O11）薄膜工艺中，通过使用在原位形成的薄的IrO 2层，铁电性能得到改善，而不损害漏电流。 通过使用Pt / Ir电极，需要相对低的MOCVD处理温度来实现c轴取向的锗酸铅（Pb5Ge3O11）薄膜。 Pt / Ir顶部的MOCVD c轴取向锗酸铅（Pb5Ge3O11）薄膜的温度范围为400-500℃。与使用单层铱电极相比，获得了较大的成核密度。 因此，锗酸铅（Pb5Ge3O11）薄膜表面光滑，微观组织均匀，铁电性能均匀。 还提供了形成上述多层电极铁电体结构体的方法。

公开(公告)号：US06531324B2

公开(公告)日：2003-03-11

申请号：US09820039

申请日：2001-03-28

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L2100

CPC分类号： H01L29/516 ,  H01L21/28291 ,  H01L29/78391

摘要： A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

公开(公告)号：US06495378B2

公开(公告)日：2002-12-17

申请号：US09814273

申请日：2001-03-21

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/02197 ,  C23C16/40 ,  H01L21/02271 ,  H01L21/31604 ,  H01L21/31691

摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.

摘要翻译： 提供Pb3GeO5相PGO薄膜。 该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。 该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。 该方法将Pd和锗在溶剂中混合。 将溶液加热以形成分解的前体蒸汽。 该方法提供沉积温度和压力。 沉积的膜也被退火以增强膜的铁弹性特征。 还提供了由本发明PGO膜制成的铁弹性电容器。

公开(公告)号：US06190925B1

公开(公告)日：2001-02-20

申请号：US09302272

申请日：1999-04-28

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/31604 ,  C23C16/40 ,  H01L21/31691 ,  Y10S438/933

摘要： The present invention provides a substantially single crystal PGO film with optimal the ferroelectric properties. The PGO film and adjacent electrodes are epitaxially grown to minimize mismatch between the structures. MOCVD deposition methods and RTP annealing procedures permit a PGO film to be epitaxially grown in commercial fabrication processes. These epitaxial ferroelectric have application in FeRAM memory devices. The present invention deposition method epitaxially grows ferroelectric Pb5Ge3O11 thin films along with c-axis orientation.

摘要翻译： 本发明提供了具有最佳铁电性能的基本单晶PGO膜。 PGO膜和相邻电极被外延生长以最小化结构之间的失配。 MOCVD沉积方法和RTP退火程序允许PGO膜在商业制造工艺中外延生长。 这些外延铁电体已经应用于FeRAM存储器件中。 本发明沉积方法外延生长铁电Pb5Ge3O11薄膜以及c轴取向。

公开(公告)号：US07112837B2

公开(公告)日：2006-09-26

申请号：US11262545

申请日：2005-10-28

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L29/76

CPC分类号： H01L27/1159 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585

摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

摘要翻译： 一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及 沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。 还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。