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    FIELD EFFECT TRANSISTOR STRUCTURE WITH ABRUPT SOURCE/DRAIN JUNCTIONS
    35.
    发明申请
    FIELD EFFECT TRANSISTOR STRUCTURE WITH ABRUPT SOURCE/DRAIN JUNCTIONS 有权
    具有冲击源/漏联结的场效应晶体管结构

    公开(公告)号：US20100133595A1

    公开(公告)日：2010-06-03

    申请号：US12700637

    申请日：2010-02-04

    申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

    摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

    摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

    Field effect transistor structure with abrupt source/drain junctions
    36.
    发明申请
    Field effect transistor structure with abrupt source/drain junctions 有权
    具有突发的源极/漏极结的场效应晶体管结构

    公开(公告)号：US20090011565A1

    公开(公告)日：2009-01-08

    申请号：US12231172

    申请日：2008-08-28

    申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

    摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

    摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

    MOS transistor structure and method of fabrication
    37.
    发明授权
    MOS transistor structure and method of fabrication 有权
    MOS晶体管结构及其制造方法

    公开(公告)号：US07391087B2

    公开(公告)日：2008-06-24

    申请号：US09475452

    申请日：1999-12-30

    申请人： Anand Murthy ,  Robert S. Chau ,  Patrick Morrow

    发明人： Anand Murthy ,  Robert S. Chau ,  Patrick Morrow

    IPC分类号： H01L27/148

    CPC分类号： H01L29/66628 ,  H01L21/28052 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636

    摘要： An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.

    摘要翻译： 一种MOS器件，包括在第一导电类型区域上形成的栅极电介质。 形成在栅极电介质上的栅电极。 沿着栅电极的横向相对的侧壁形成一对侧壁间隔物。 一对沉积的硅或硅合金源极/漏极区域形成在栅电极的第一导电区域和相对侧上，其中硅或硅合金源极/漏极区域在栅极电极下方延伸并且限定在栅电极下方的沟道区域 第一导电类型区域中的栅极电极，其中栅电极正下方的沟道区域大于深入所述第一导电类型区域的沟道区域。

    FORMING ULTRA DENSE 3-D INTERCONNECT STRUCTURES
    38.
    发明申请
    FORMING ULTRA DENSE 3-D INTERCONNECT STRUCTURES 有权
    形成超声DENSE 3-D互连结构

    公开(公告)号：US20070145601A1

    公开(公告)日：2007-06-28

    申请号：US11673375

    申请日：2007-02-09

    申请人： Patrick Morrow

    发明人： Patrick Morrow

    IPC分类号： H01L23/48

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01327 ,  H01L2924/00

    摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include bonding at least one bond pad of a device side of a first substrate to at least one bond pad of a device side of a second substrate, forming at least one via to connect to at least one of an active feature and an interconnect structure disposed within the first substrate, and forming a reactive material on a surface of at least one of the active features.

    摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括将第一衬底的器件侧的至少一个焊盘焊接到第二衬底的器件侧的至少一个接合焊盘，形成至少一个通孔，以连接至活性特征和 布置在所述第一基板内的互连结构，以及在至少一个所述有源特征的表面上形成反应性材料。