公开(公告)号：US20100271860A1

公开(公告)日：2010-10-28

申请号：US12745300

申请日：2009-09-30

申请人： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

发明人： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0033 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34

摘要： A method of driving a variable resistance element includes: a writing step performed by applying a writing voltage pulse having a first polarity to a variable resistance layer to change a resistance state of the layer from high to low; and an erasing step performed by applying an erasing voltage pulse having a second polarity to the layer to change the state from low to high. Here, |Vw1|>|Vw2| where Vw1 represents a voltage value of the writing voltage pulse for first to N-th writing steps (N≧1) and Vw2 represents a voltage value of the writing voltage pulse for (N+1)-th and subsequent writing steps, and |Ve1|>|Ve2| where Ve1 represents a voltage value of the erasing voltage pulse for first to M-th erasing steps (M≧1) and Ve2 represents a voltage value of the erasing voltage pulse for (M+1)-th and subsequent erasing steps. The (N+1)-th writing step follows the M-th erasing step.

摘要翻译： 驱动可变电阻元件的方法包括：通过将具有第一极性的写入电压脉冲施加到可变电阻层而将层的电阻状态从高变为低的步骤来执行写入步骤; 以及通过将具有第二极性的擦除电压脉冲施加到该层以将状态从低变为高而执行的擦除步骤。 这里，| Vw1 |> | Vw2 | 其中Vw1表示第一至第N写入步骤（N≥1）的写入电压脉冲的电压值，Vw2表示第（N + 1）个和后续写入步骤中的写入电压脉冲的电压值， Ve1 |> | Ve2 | 其中Ve1表示第一至第M擦除步骤（M≥1）的擦除电压脉冲的电压值，Ve2表示（M + 1）次和随后的擦除步骤中的擦除电压脉冲的电压值。 第（N + 1）个写入步骤在第M擦除步骤之后。

公开(公告)号：US08395930B2

公开(公告)日：2013-03-12

申请号：US13596154

申请日：2012-08-28

申请人： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

发明人： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A method includes applying a first polarity writing voltage pulse to a metal oxide layer to change its resistance state from high to low into a write state, applying a second polarity erasing voltage pulse different from the first polarity to the metal oxide layer to change its resistance state from low to high into an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer before first application of the writing voltage pulse, to change an initial resistance value of the metal oxide layer. R0>RH>RL and |V0|>|Ve|≧|Vw| are satisfied where R0, RL, and RH are the resistance values of the initial, write, and erase states, respectively, of the metal oxide layer, and V0, Vw, and Ve are voltage values of the initial, writing, and erasing voltage pulses, respectively.

摘要翻译： 一种方法包括：将第一极性写入电压脉冲施加到金属氧化物层，以将其电阻状态从高变为低电平变为写入状态，将不同于第一极性的第二极性擦除电压脉冲施加到金属氧化物层以改变其电阻 状态从低到高进入擦除状态，以及在首次施加写入电压脉冲之前将具有第二极性的初始电压脉冲施加到金属氧化物层，以改变金属氧化物层的初始电阻值。 R0> RH> RL和| V0 |> | Ve |≥| Vw | 满足R0，RL和RH分别是金属氧化物层的初始，写入和擦除状态的电阻值，V0，Vw和Ve是初始，写入和擦除电压的电压值 脉冲。

公开(公告)号：US08279658B2

公开(公告)日：2012-10-02

申请号：US12994462

申请日：2010-03-25

申请人： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

发明人： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： Applying a writing voltage pulse having a first polarity to a metal oxide layer (3) to change a resistance state of the metal oxide layer (3) from high to low so as to render the resistance state a write state, applying an erasing voltage pulse having a second polarity different from the first polarity to the metal oxide layer (3) to change the resistance state of the metal oxide layer (3) from low to high so as to render the resistance state an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer (3) before the applying of a writing voltage pulse is performed for a first time, to change a resistance value of an initial state of the metal oxide layer (3) are included, and R0>RH>RL and |V0|>|Ve|≧|Vw| are satisfied where R0, RL, and RH are the resistance values of the initial, write, and erase states, respectively, of the metal oxide layer (3), and V0, Vw, and Ve are voltage values of the initial, writing, and erasing voltage pulses, respectively.

摘要翻译： 将具有第一极性的写入电压脉冲施加到金属氧化物层（3）以将金属氧化物层（3）的电阻状态从高变为低，以使电阻状态成为写入状态，施加擦除电压脉冲 具有与第一极性不同于金属氧化物层（3）的第二极性，以将金属氧化物层（3）的电阻状态从低到高改变为使得电阻状态为擦除状态，并且施加初始电压 首先执行施加写入电压脉冲之前对金属氧化物层（3）具有第二极性的脉冲，以改变金属氧化物层（3）的初始状态的电阻值，并且R0 > RH> RL和| V0 |> | Ve |≥| Vw | 满足R0，RL和RH分别为金属氧化物层（3）的初始，写入和擦除状态的电阻值，V0，Vw和Ve为初始，写入和写入的电压值， 并分别擦除电压脉冲。

公开(公告)号：US20100321982A1

公开(公告)日：2010-12-23

申请号：US12867392

申请日：2009-12-16

申请人： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

发明人： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

摘要： To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . . ) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . . ) and bit lines (BL0, BL1, . . . ) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . . ); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . . ); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).

摘要翻译： 提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。 非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。

公开(公告)号：US08619460B2

公开(公告)日：2013-12-31

申请号：US13509616

申请日：2011-10-26

申请人： Yoshihiko Kanzawa ,  Takeshi Takagi

发明人： Yoshihiko Kanzawa ,  Takeshi Takagi

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2213/56 ,  G11C2213/76

摘要： A nonvolatile memory device (800) includes a variable resistance nonvolatile memory element (100) and a control circuit (810). The control circuit (810) determines whether a resistance value of the nonvolatile memory element (100) in a high resistance state is equal to or greater than a predetermined threshold value. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is smaller than the threshold value, the control circuit (810) applies a first voltage (VL1) to the nonvolatile memory element (100) to change a resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is equal to or greater than the threshold value, the control circuit (810) applies to the nonvolatile memory element (100) a second voltage (VL2) an absolute value of which is smaller an absolute value of the first voltage (VL1) to change the resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state.

摘要翻译： 非易失性存储器件（800）包括可变电阻非易失性存储元件（100）和控制电路（810）。 控制电路（810）确定高电阻状态下的非易失性存储元件（100）的电阻值是否等于或大于预定阈值。 此外，如果高电阻状态下的非易失性存储元件（100）的电阻值小于阈值，则控制电路（810）向非易失性存储元件（100）施加第一电压（VL1） 非易失性存储元件（100）从高电阻状态到低电阻状态的电阻状态。 此外，如果高电阻状态下的非易失性存储元件（100）的电阻值为阈值以上，则控制电路（810）向非易失性存储元件（100）施加第二电压（VL2） 其绝对值对于将非易失性存储元件（100）的电阻状态从高电阻状态改变为低电阻状态的第一电压（VL1）的绝对值较小。

公开(公告)号：US20130037775A1

公开(公告)日：2013-02-14

申请号：US13567646

申请日：2012-08-06

申请人： Satoru Mitani ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Takeshi Takagi

发明人： Satoru Mitani ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Takeshi Takagi

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9≦x≦1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8≦y≦2.0) are stacked together.

摘要翻译： 本发明的非易失性存储元件包括第一电极（103），第二电极（108） 介于第一电极（103）和第二电极（107）之间的电阻变化层（107），其被配置成响应于施加在电极（103）和（108）之间的电信号可逆地切换电阻值， ，并且电阻变化层（107）具有至少多层结构，其中具有表示为HfO x（0.9＆nlE; x＆nlE; 1.6）的组成的第一含铪层和具有组成的第二含铪层 表示为HfOy（1.8＆nlE; y＆nlE; 2.0）堆叠在一起。

公开(公告)号：US20130010522A1

公开(公告)日：2013-01-10

申请号：US13509616

申请日：2011-10-26

申请人： Yoshihiko Kanzawa ,  Takeshi Takagi

发明人： Yoshihiko Kanzawa ,  Takeshi Takagi

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2213/56 ,  G11C2213/76

摘要： A nonvolatile memory device (800) includes a variable resistance nonvolatile memory element (100) and a control circuit (810). The control circuit (810) determines whether a resistance value of the nonvolatile memory element (100) in a high resistance state is equal to or greater than a predetermined threshold value. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is smaller than the threshold value, the control circuit (810) applies a first voltage (VL1) to the nonvolatile memory element (100) to change a resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is equal to or greater than the threshold value, the control circuit (810) applies to the nonvolatile memory element (100) a second voltage (VL2) an absolute value of which is smaller an absolute value of the first voltage (VL1) to change the resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state.

摘要翻译： 非易失性存储器件（800）包括可变电阻非易失性存储元件（100）和控制电路（810）。 控制电路（810）确定高电阻状态下的非易失性存储元件（100）的电阻值是否等于或大于预定阈值。 此外，如果高电阻状态下的非易失性存储元件（100）的电阻值小于阈值，则控制电路（810）向非易失性存储元件（100）施加第一电压（VL1） 非易失性存储元件（100）从高电阻状态到低电阻状态的电阻状态。 此外，如果高电阻状态下的非易失性存储元件（100）的电阻值为阈值以上，则控制电路（810）向非易失性存储元件（100）施加第二电压（VL2） 其绝对值对于将非易失性存储元件（100）的电阻状态从高电阻状态改变为低电阻状态的第一电压（VL1）的绝对值较小。

公开(公告)号：US08320159B2

公开(公告)日：2012-11-27

申请号：US12993706

申请日：2010-03-15

申请人： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

发明人： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series. Each of the memory cells is configured such that the control terminal is a part of a first wire (WL) associated with the memory cell or is connected to the first wire associated with the memory cell, the second electrode is a part of a second wire (SL) associated with the memory cell or is connected to the second wire associated with the memory cell; and the first electrode is a part of a series path (SP) associated with the memory cell or is connected to the series path associated with the memory cell.

摘要翻译： 每个存储单元（MC）包括一个晶体管和一个电阻可变元件。 晶体管包括第一主端子，第二主端子和控制端子。 电阻可变元件包括设置在第一电极和第二电极之间的第一电极，第二电极和电阻变化层。 两个相邻存储单元之一的第一主端子连接到另一个存储单元的第二主端子，以形成串联连接多个存储单元的主端子的串行路径（SP）。 每个存储器单元被配置为使得控制端子是与存储器单元相关联的第一布线（WL）的一部分或者连接到与存储单元相关联的第一布线，第二电极是第二布线 （SL），或者连接到与存储器单元相关联的第二线; 并且第一电极是与存储器单元相关联的或连接到与存储器单元相关联的串联路径的串联路径（SP）的一部分。

公开(公告)号：US20110244645A1

公开(公告)日：2011-10-06

申请号：US13162310

申请日：2011-06-16

申请人： Junko IWANAGA ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

发明人： Junko IWANAGA ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US07986002B2

公开(公告)日：2011-07-26

申请号：US10549291

申请日：2004-03-19

申请人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

发明人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC分类号： H01L29/66

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。