公开(公告)号：US20100321982A1

公开(公告)日：2010-12-23

申请号：US12867392

申请日：2009-12-16

申请人： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

发明人： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

摘要： To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . . ) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . . ) and bit lines (BL0, BL1, . . . ) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . . ); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . . ); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).

摘要翻译： 提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。 非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。

公开(公告)号：US08125817B2

公开(公告)日：2012-02-28

申请号：US12867392

申请日：2009-12-16

申请人： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

发明人： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C11/34 ,  G11C5/14 ,  G11C7/00

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

摘要： To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . .) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . .) and bit lines (BL0, BL1, . . .) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . .); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . .); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).

摘要翻译： 提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。 非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。

公开(公告)号：US08305795B2

公开(公告)日：2012-11-06

申请号：US12999019

申请日：2010-04-27

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

摘要： To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element (10a) to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element (10a) to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step (408), thereby setting the variable resistance element (10a) through the low resistance state to the high resistance state (401).

摘要翻译： 为了提供可变电阻元件写入方法，即使当可变电阻元件具有成为半LR状态的可能性时，通过将可变电阻元件校正为正常的低电阻状态来确保最大电阻变化窗口。 在根据施加电压的极性将数据写入到可变电阻元件（10a）的方法中，可变电阻元件（10a）根据施加电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为施加到上电极（11）的电压相对于 下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件（10a）设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件（10a）设置为低电阻状态（403,402）; 并且在低电阻写入步骤（408）中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件（10a）设置为低电阻状态为高电阻 州（401）。

公开(公告)号：US20110122680A1

公开(公告)日：2011-05-26

申请号：US13054312

申请日：2010-04-14

申请人： Yuuichirou Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Yuuichirou Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/12 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

摘要： A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.

摘要翻译： 一种非易失性电阻可变存储器件（100）包括存储单元（M11，M12 ...），每个存储单元包括可变电阻元件（R11，R12 ...），该可变电阻元件（R11，R12 ...） 第一电极和第二电极，以及包括放置在第三电极和第四电极之间并与第三电极和第四电极接触的电流导向层的电流导向元件（D11，D12 ...）串联连接，并且驱动该装置 通过第一LR驱动电路（105a1）经由限流电路（105b），以在器件被第二HR驱动电路（105a2）驱动时降低可变电阻元件的电阻，以增加可变电阻元件的电阻，从而使用 电流限制电路（105b），用于使可变电阻元件的电阻降低的电流低于用于增加可变电阻元件的电阻的电流。

公开(公告)号：US08325508B2

公开(公告)日：2012-12-04

申请号：US13001905

申请日：2010-06-08

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/00

CPC分类号： G11C11/5685 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/79

摘要： A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value. At the HR writing step (S51a), a voltage pulse having a voltage Vp that is equal to or higher than the first voltage V1 and equal to or lower than the second voltage V2 is applied to the variable resistance element, thereby changing the variable resistance element from the low resistance state (S52) to the high resistance state (S53).

摘要翻译： 提供了一种最佳可变电阻元件的写入方法，其可以使可变电阻元件的操作窗口最大化。 对于根据施加的电压脉冲的极性在高电阻状态和低电阻状态之间可逆地变化的可变电阻元件执行写入方法。 写入方法包括准备步骤（S50）和写入步骤（S51，S51a，S51b）。 在准备步骤（S50）中，通过向可变电阻元件施加逐渐增加的电压的电压脉冲来测量可变电阻元件的电阻值，从而确定用于开始高电阻写入的第一电压V1和具有 最大电阻值。 在HR写入步骤（S51a）中，将具有等于或高于第一电压V1并且等于或低于第二电压V2的电压Vp的电压脉冲施加到可变电阻元件，从而改变可变电阻 元件从低电阻状态（S52）到高电阻状态（S53）。

公开(公告)号：US08665633B2

公开(公告)日：2014-03-04

申请号：US13599406

申请日：2012-08-30

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

摘要： A method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step, thereby setting the variable resistance element through the low resistance state to the high resistance state.

摘要翻译： 根据施加电压的极性将数据写入可变电阻元件（10a）的方法，该可变电阻元件（10a）根据施加的电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为对上电极（11）相对于 下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件设置为低电阻状态（403,402）; 并且在低电阻写入步骤中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件通过低电阻状态设置为高电阻状态。

公开(公告)号：US20110128773A1

公开(公告)日：2011-06-02

申请号：US12999019

申请日：2010-04-27

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

摘要： To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element (10a) to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element (10a) to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step (408), thereby setting the variable resistance element (10a) through the low resistance state to the high resistance state (401).

摘要翻译： 为了提供可变电阻元件写入方法，即使当可变电阻元件具有成为半LR状态的可能性时，通过将可变电阻元件校正为正常的低电阻状态来确保最大电阻变化窗口。 在根据施加电压的极性将数据写入到可变电阻元件（10a）的方法中，可变电阻元件（10a）根据施加电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为施加到上电极（11）的电压相对于 下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件（10a）设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件（10a）设置为低电阻状态（403,402）; 并且在低电阻写入步骤（408）中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件（10a）设置为低电阻状态为高电阻 州（401）。

公开(公告)号：US08441837B2

公开(公告)日：2013-05-14

申请号：US13054312

申请日：2010-04-14

申请人： Yuuichirou Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Yuuichirou Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/12 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

摘要： A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.

摘要翻译： 一种非易失性电阻可变存储器件（100）包括存储单元（M11，M12 ...），每个存储单元包括可变电阻元件（R11，R12 ...），该可变电阻元件（R11，R12 ...） 第一电极和第二电极，以及包括放置在第三电极和第四电极之间并与第三电极和第四电极接触的电流导向层的电流导向元件（D11，D12 ...）串联连接，并且驱动该装置 通过第一LR驱动电路（105a1）经由限流电路（105b），以在器件被第二HR驱动电路（105a2）驱动时降低可变电阻元件的电阻，以增加可变电阻元件的电阻，从而使用 电流限制电路（105b），用于使可变电阻元件的电阻降低的电流低于用于增加可变电阻元件的电阻的电流。

公开(公告)号：US20120120712A1

公开(公告)日：2012-05-17

申请号：US13001943

申请日：2010-06-04

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/00 ,  H01L21/8239

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： An optimum forming method of performing a forming for a variable resistance element to maximize an operation window of the variable resistance element is provided. The forming method is used to initialize a variable resistance element (100). The forming method includes: a determination step (S35) of determining whether or not a current resistance value of the variable resistance element (100) is lower than a resistance value in a high resistance state; and a voltage application step (S36) of applying a voltage pulse having a voltage not exceeding a sum of a forming voltage and a forming margin when the determination is made that the current resistance value is not lower than the resistance value in the high resistance state (No at S35). The determination step (S35) and the voltage application step (S36) are repeated to process all memory cells in a memory array (202) (S34 to S37).

摘要翻译： 提供了一种用于对可变电阻元件进行成形以最大化可变电阻元件的操作窗口的最佳形成方法。 成形方法用于初始化可变电阻元件（100）。 形成方法包括：确定可变电阻元件（100）的当前电阻值是否低于高电阻状态下的电阻值的确定步骤（S35） 以及当确定当前电阻值不低于高电阻状态下的电阻值时，施加具有不超过形成电压和形成余量之和的电压的电压脉冲的电压施加步骤（S36） （S35否）。 重复确定步骤（S35）和电压施加步骤（S36）以处理存储器阵列（202）中的所有存储器单元（S34至S37）。

公开(公告)号：US08395925B2

公开(公告)日：2013-03-12

申请号：US13001943

申请日：2010-06-04

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： An optimum forming method of performing a forming for a variable resistance element to maximize an operation window of the variable resistance element is provided. The forming method is used to initialize a variable resistance element (100). The forming method includes: a determination step (S35) of determining whether or not a current resistance value of the variable resistance element (100) is lower than a resistance value in a high resistance state; and a voltage application step (S36) of applying a voltage pulse having a voltage not exceeding a sum of a forming voltage and a forming margin when the determination is made that the current resistance value is not lower than the resistance value in the high resistance state (No at S35). The determination step (S35) and the voltage application step (S36) are repeated to process all memory cells in a memory array (202) (S34 to S37).

摘要翻译： 提供了一种用于对可变电阻元件进行成形以最大化可变电阻元件的操作窗口的最佳形成方法。 成形方法用于初始化可变电阻元件（100）。 形成方法包括：确定可变电阻元件（100）的当前电阻值是否低于高电阻状态下的电阻值的确定步骤（S35） 以及当确定当前电阻值不低于高电阻状态下的电阻值时，施加具有不超过形成电压和形成余量之和的电压的电压脉冲的电压施加步骤（S36） （S35否）。 重复确定步骤（S35）和电压施加步骤（S36）以处理存储器阵列（202）中的所有存储器单元（S34至S37）。