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    Nonvolatile storage device and method for writing into the same
    1.
    发明授权
    Nonvolatile storage device and method for writing into the same 有权
    非易失存储装置及其写入方法

    公开(公告)号：US08125817B2

    公开(公告)日：2012-02-28

    申请号：US12867392

    申请日：2009-12-16

    申请人： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

    发明人： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

    IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C11/34 ,  G11C5/14 ,  G11C7/00

    CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

    摘要： To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . .) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . .) and bit lines (BL0, BL1, . . .) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . .); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . .); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).

    摘要翻译： 提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。 非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。

    NONVOLATILE STORAGE DEVICE AND METHOD FOR WRITING INTO THE SAME
    2.
    发明申请
    NONVOLATILE STORAGE DEVICE AND METHOD FOR WRITING INTO THE SAME 有权
    非易失存储器件及其写入方法

    公开(公告)号：US20100321982A1

    公开(公告)日：2010-12-23

    申请号：US12867392

    申请日：2009-12-16

    申请人： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

    发明人： Takeshi Takagi ,  Shunsaku Muraoka ,  Ryotaro Azuma ,  Kunitoshi Aono

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

    摘要： To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . . ) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . . ) and bit lines (BL0, BL1, . . . ) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . . ); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . . ); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).

    摘要翻译： 提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。 非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。

    NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE
    3.
    发明申请
    NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE 有权
    非易失性存储元件和非易失性存储器件

    公开(公告)号：US20120327702A1

    公开(公告)日：2012-12-27

    申请号：US13599286

    申请日：2012-08-30

    申请人： Takeshi Takagi ,  Zhiqiang Wei ,  Takeki Ninomiya ,  Shunsaku Muraoka ,  Yoshihiko Kanzawa

    发明人： Takeshi Takagi ,  Zhiqiang Wei ,  Takeki Ninomiya ,  Shunsaku Muraoka ,  Yoshihiko Kanzawa

    IPC分类号： H01L45/00 ,  G11C11/21

    CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

    摘要： A nonvolatile memory element includes: a first electrode layer; a second electrode layer; and a variable resistance layer which is placed between the electrode layers, and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a polarity of a voltage applied between the electrode layers. The variable resistance layer is formed by stacking a first oxide layer including an oxide of a first transition metal and a second oxide layer including an oxide of a second transition metal which is different from the first transition metal. At least one of the following conditions is satisfied: (1) a dielectric constant of the second oxide layer is larger than a dielectric constant of the first oxide layer; and (2) a band gap of the second oxide layer is smaller than a band gap of the first oxide layer.

    摘要翻译： 非易失性存储元件包括：第一电极层; 第二电极层; 以及可变电阻层，其设置在电极层之间，并且其电阻状态基于施加在电极层之间的电压的极性而在高电阻状态和低电阻状态之间可逆地变化。 可变电阻层通过堆叠包括第一过渡金属的氧化物的第一氧化物层和包含与第一过渡金属不同的第二过渡金属的氧化物的第二氧化物层而形成。 满足以下条件中的至少一个：（1）第二氧化物层的介电常数大于第一氧化物层的介电常数; 和（2）第二氧化物层的带隙小于第一氧化物层的带隙。

    METHOD OF PROGRAMMING VARIABLE RESISTANCE ELEMENT AND NONVOLATILE STORAGE DEVICE
    4.
    发明申请
    METHOD OF PROGRAMMING VARIABLE RESISTANCE ELEMENT AND NONVOLATILE STORAGE DEVICE 有权
    可变电阻元件和非易失性存储器件的编程方法

    公开(公告)号：US20120320661A1

    公开(公告)日：2012-12-20

    申请号：US13596154

    申请日：2012-08-28

    申请人： Shunsaku MURAOKA ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

    发明人： Shunsaku MURAOKA ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

    摘要： A method includes applying a first polarity writing voltage pulse to a metal oxide layer to change its resistance state from high to low into a write state, applying a second polarity erasing voltage pulse different from the first polarity to the metal oxide layer to change its resistance state from low to high into an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer before first application of the writing voltage pulse, to change an initial resistance value of the metal oxide layer. R0>RH>RL and |V0|>|Ve|≧|Vw| are satisfied where R0, RL, and RH are the resistance values of the initial, write, and erase states, respectively, of the metal oxide layer, and V0, Vw, and Ve are voltage values of the initial, writing, and erasing voltage pulses, respectively.

    摘要翻译： 一种方法包括：将第一极性写入电压脉冲施加到金属氧化物层，以将其电阻状态从高变为低电平变为写入状态，将不同于第一极性的第二极性擦除电压脉冲施加到金属氧化物层以改变其电阻 状态从低到高进入擦除状态，以及在首次施加写入电压脉冲之前将具有第二极性的初始电压脉冲施加到金属氧化物层，以改变金属氧化物层的初始电阻值。 R0> RH> RL和| V0 |> | Ve |≥| Vw | 满足R0，RL和RH分别是金属氧化物层的初始，写入和擦除状态的电阻值，V0，Vw和Ve是初始，写入和擦除电压的电压值 脉冲。

    METHOD FOR DRIVING NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY DEVICE
    6.
    发明申请
    METHOD FOR DRIVING NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY DEVICE 有权
    用于驱动非易失性存储器元件的方法和非易失性存储器件

    公开(公告)号：US20140029330A1

    公开(公告)日：2014-01-30

    申请号：US14004447

    申请日：2012-03-13

    申请人： Shunsaku Muraoka ,  Satoru Mitani ,  Takeshi Takagi

    发明人： Shunsaku Muraoka ,  Satoru Mitani ,  Takeshi Takagi

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    摘要： A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR

    摘要翻译： 一种用于驱动非易失性存储元件的方法包括：通过施加具有第一极性的写入电压脉冲将可变电阻层改变为低电阻状态的写入步骤; 以及通过施加具有与第一极性不同的第二极性的擦除电压脉冲将可变电阻层改变为高电阻状态的擦除步骤，其中在写入步骤中，场效应晶体管的第一输入和输出端子是 晶体管的源极端子，并且当写入电压脉冲的脉冲宽度为PWLR且擦除电压脉冲的脉冲宽度为PWHR时，PWLR和PWHR满足PWLR

    Nonvolatile storage device and method for writing into memory cell of the same
    9.
    发明授权
    Nonvolatile storage device and method for writing into memory cell of the same 有权
    非易失性存储装置和写入其中的存储单元的方法

    公开(公告)号：US08179714B2

    公开(公告)日：2012-05-15

    申请号：US12865193

    申请日：2009-10-16

    申请人： Takeshi Takagi ,  Shunsaku Muraoka ,  Mitsuteru Iijima ,  Ken Kawai ,  Kazuhiko Shimakawa

    发明人： Takeshi Takagi ,  Shunsaku Muraoka ,  Mitsuteru Iijima ,  Ken Kawai ,  Kazuhiko Shimakawa

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

    摘要： Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array (202) which includes memory cells (M11) or the like each of which includes a variable resistance element (R11) and a transistor (N11) that are formed above the semiconductor substrate (301) and connected in series; and a substrate bias circuit (220) which applies, to the P-type well (301a), a bias voltage in a forward direction with respect to a source and a drain of the transistor (N11), when a voltage pulse for writing is applied to the variable resistance element (R11) included in the selected memory cell (M11) or the like.

    摘要翻译： 提供一种能够在不增加包含在每个存储单元中的选择晶体管的尺寸的情况下稳定地工作的非易失性存储装置（200）。 非易失性存储装置（200）包括：具有第一导电型的P型阱（301a）的半导体基板（301） 存储单元阵列（202），其包括存储单元（M11）等，每个存储单元包括形成在半导体衬底（301）上并串联连接的可变电阻元件（R11）和晶体管（N11）; 以及衬底偏置电路（220），当用于写入的电压脉冲为写入电压脉冲时，向P型阱（301a）施加相对于晶体管（N11）的源极和漏极的正向偏置电压 应用于所选择的存储单元（M11）等中包含的可变电阻元件（R11）。