公开(公告)号：US20230170855A1

公开(公告)日：2023-06-01

申请号：US17539090

申请日：2021-11-30

Applicant: Silicon Laboratories Inc.

Inventor： Diptendu Ghosh ,  Mustafa H. Koroglu ,  Dayasagar Gaade ,  Francesco Barale

IPC: H03F3/217 ,  H03L7/081

CPC classification number: H03F3/217 ,  H03L7/0812 ,  H03F2200/165 ,  H03K19/20

Abstract: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.

公开(公告)号：US20220085787A1

公开(公告)日：2022-03-17

申请号：US17537075

申请日：2021-11-29

Applicant: Silicon Laboratories Inc.

Inventor： Vitor Pereira ,  Jeffrey A. Tindle ,  Mustafa H. Koroglu ,  Terry Lee Dickey

IPC: H03H7/01 ,  H04B1/18 ,  H04B1/04 ,  H04B1/40

Abstract: A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.

公开(公告)号：US20210175870A1

公开(公告)日：2021-06-10

申请号：US16706433

申请日：2019-12-06

Applicant: Silicon Laboratories Inc.

Inventor： Vitor Pereira ,  Jeffrey A. Tindle ,  Mustafa H. Koroglu ,  Terry Lee Dickey

IPC: H03H7/01 ,  H04B1/18 ,  H04B1/04 ,  H04B1/40

Abstract: A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.

公开(公告)号：US10256854B1

公开(公告)日：2019-04-09

申请号：US15875278

申请日：2018-01-19

Applicant: Silicon Laboratories Inc.

Inventor： Rangakrishnan Srinivasan ,  Sriharsha Vasadi ,  Zhongda Wang ,  Mustafa H. Koroglu ,  John M. Khoury ,  Aslamali A. Rafi ,  Michael S. Johnson ,  Francesco Barale ,  Sherry Xiaohong Wu

IPC: H04B1/04 ,  H03F3/195 ,  H03F3/213 ,  H03F3/45 ,  H03K3/017 ,  H03F1/32 ,  H03K3/0231

Abstract: In an embodiment, an apparatus includes: a transmit circuit to upconvert a baseband signal to a first differential radio frequency (RF) signal, the transmit circuit to convert the first differential RF signal to a first single-ended RF signal; a duty cycle correction circuit coupled to the transmit circuit to receive the first single-ended RF signal and compensate for a duty cycle variation in the first single-ended RF signal to output a duty cycle-corrected RF signal; a conversion circuit to convert the duty cycle-corrected RF signal to a second differential RF signal; and an interface circuit to transfer the second differential RF signal from a first ground domain to a second ground domain.

公开(公告)号：US09712176B1

公开(公告)日：2017-07-18

申请号：US15179847

申请日：2016-06-10

Applicant: Silicon Laboratories Inc.

Inventor： Aslamali A. Rafi ,  Mustafa H. Koroglu

IPC: H03L7/06 ,  H03L7/183 ,  H04L7/033 ,  H04B7/02

CPC classification number: H03L7/0893 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18 ,  H03L2207/06

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is lower than the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

公开(公告)号：US09407276B1

公开(公告)日：2016-08-02

申请号：US14747057

申请日：2015-06-23

Applicant: Silicon Laboratories Inc.

Inventor： Abdulkerim L. Coban ,  Mustafa H. Koroglu

IPC: H03M1/06 ,  H03M1/00 ,  H03M1/10 ,  H03M1/12

CPC classification number: H03M1/002 ,  H03M1/0626 ,  H03M1/1009 ,  H03M1/124 ,  H03M1/60

Abstract: In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value.

Abstract translation: 在一个实施例中，一种装置包括：第一压控振荡器（VCO）模数转换器（ADC）单元，用于接收差分模拟信号的第一部分，并将差分模拟信号的第一部分转换成第一数字 值; 第二VCO ADC单元，用于接收差分模拟信号的第二部分，并将差分模拟信号的第二部分转换为第二数字值; 组合器，用于从第一和第二数字值形成组合的数字信号; 一个抽取电路，用于接收组合的数字信号，并将组合的数字信号滤波成经滤波的组合数字信号; 以及抵消电路，用于至少部分地基于系数值接收经滤波的组合数字信号并产生失真消除的数字信号。

公开(公告)号：US20160056845A1

公开(公告)日：2016-02-25

申请号：US14930139

申请日：2015-11-02

Applicant: Silicon Laboratories Inc.

Inventor： Mustafa H. Koroglu ,  Yu Su

IPC: H04B1/00 ,  H03F1/56 ,  H03F3/193 ,  H04B1/16

CPC classification number: H04B1/005 ,  H03F1/565 ,  H03F3/19 ,  H03F3/193 ,  H03F2200/171 ,  H03F2200/294 ,  H03F2200/451 ,  H03H7/0169 ,  H03H7/09 ,  H03H7/46 ,  H03H11/1291 ,  H03H2210/025 ,  H03H2210/033 ,  H03J3/10 ,  H03J2200/32 ,  H04B1/16 ,  H04B1/1638 ,  H04B1/18

Abstract: A receiver includes a first amplifier having an input for receiving a radio frequency (RF) signal, and an output for providing an amplified RF signal, a switch section for selectively switching the RF signal onto one of a plurality of nodes, and a filter section comprising a plurality of filters coupled to respective ones of the plurality of nodes. A first filter of the plurality of filters comprises a first variable capacitor coupled in parallel with an inductance leg between a corresponding one of the plurality of nodes and a power supply voltage terminal, wherein the first variable capacitor has a capacitance that varies in response to a tuning signal, and the inductance leg comprises a first inductorin series with an effective resistance, wherein the effective resistance has a value related to an upper cutoff frequency to be tuned by the first filter.

Abstract translation: 接收机包括具有用于接收射频（RF）信号的输入端和用于提供放大的RF信号的输出的第一放大器，用于选择性地将RF信号切换到多个节点之一的开关部分，以及滤波器部分 包括耦合到所述多个节点中的相应节点的多个滤波器。 多个滤波器的第一滤波器包括与多个节点中的相应一个节点之间的电感支路并联耦合的第一可变电容器和电源电压端子，其中第一可变电容器具有响应于 调谐信号，并且电感腿包括具有有效电阻的第一电感器串联，其中有效电阻具有与要由第一滤波器调谐的上截止频率相关的值。

公开(公告)号：US20150147992A1

公开(公告)日：2015-05-28

申请号：US14612346

申请日：2015-02-03

Applicant: Silicon Laboratories Inc.

Inventor： Ramin Khoini-Poorfard ,  Alessandro Piovaccari ,  Aslamali A. Rafi ,  Mustafa H. Koroglu ,  David S. Trager ,  Abdulkerim L. Coban

IPC: H04B1/28 ,  H04L27/148

CPC classification number: H04B1/28 ,  H03H11/04 ,  H04B1/30 ,  H04L27/148 ,  H04N5/455 ,  H04N5/50

Abstract: In one form, an integrated receiver includes a tracking bandpass filter, a tunable lowpass filter, and a mixer formed on a single integrated circuit chip. The tracking bandpass filter has an input for receiving a radio frequency (RF) input signal, and an output, and comprises a variable capacitor having a capacitance that varies in response to a bandpass frequency control signal, in parallel with an integrated inductor. The integrated inductor comprises a plurality of windings formed in a plurality of metal layers. The tunable lowpass filter has an input coupled to the output of the tracking bandpass filter, and an output and having a tuning input for receiving a cutoff frequency signal. The mixer has a signal input coupled to the output of the tunable lowpass filter, a local oscillator input for receiving a local oscillator signal, and a signal output for providing a converted RF signal.

Abstract translation: 在一种形式中，集成接收器包括跟踪带通滤波器，可调谐低通滤波器和形成在单个集成电路芯片上的混频器。 跟踪带通滤波器具有用于接收射频（RF）输入信号和输出的输入，并且包括与集成电感器并联的具有响应于带通频率控制信号而变化的电容的可变电容器。 集成电感器包括形成在多个金属层中的多个绕组。 可调谐低通滤波器具有耦合到跟踪带通滤波器的输出的输入端和输出端，并具有用于接收截止频率信号的调谐输入端。 混频器具有耦合到可调谐低通滤波器的输出的信号输入，用于接收本地振荡器信号的本地振荡器输入和用于提供经转换的RF信号的信号输出。

公开(公告)号：US20150123714A1

公开(公告)日：2015-05-07

申请号：US14074241

申请日：2013-11-07

Applicant: SILICON LABORATORIES INC.

Inventor： Ruifeng Sun ,  Mustafa H. Koroglu ,  Ramin Khoini Poorfard ,  Yu Su ,  Krishna Pentakota ,  Pio Balmelli

IPC: H03K17/16

CPC classification number: H03K17/16 ,  H03K2217/0063

Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.

Abstract translation: 与缓冲电路有关的技术。 在一个实施例中，电路包括配置为源极跟随器的第一晶体管和耦合到第一晶体管的栅极端子和第一晶体管的漏极端子的前馈通路。 在该实施例中，前馈路径包括被配置为将前馈路径与输入信号的DC分量去耦到第一晶体管的栅极端子的电路。 在该实施例中，电路被配置为基于输入信号来减小第一晶体管的漏 - 源电压。 在一些实施例中，前馈路径包括配置为源极跟随器的第二晶体管，并且第二晶体管的源极端子耦合到第一晶体管的漏极端子。 在各种实施例中，减小漏极 - 源极电压可以提高第一晶体管的线性。

公开(公告)号：US08885106B2

公开(公告)日：2014-11-11

申请号：US13799384

申请日：2013-03-13

Applicant: Silicon Laboratories Inc.

Inventor： Mustafa H. Koroglu ,  Abdulkerim L. Coban

IPC: H04N5/44 ,  H04N5/50 ,  H04N5/46

CPC classification number: H04N5/4401 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4263 ,  H04N21/4382

Abstract: An apparatus includes a splitter to receive a radio frequency (RF) signal and to provide the RF signal to multiple channels of a tuner. Each channel may include an amplifier to amplify the RF signal, a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, where each of the channels is configured to receive a different LO signal, a filter to filter the downconverted second frequency signal, and a digitizer to digitize the downconverted second frequency signal. A clock generation circuit has multiple interpolative dividers and a frequency synthesizer to generate a reference clock signal. Each of the interpolative dividers is configured to receive the reference clock signal, generate a corresponding LO signal, and provide the corresponding LO signal to the mixer of at least one of the channels.

Abstract translation: 一种装置包括用于接收射频（RF）信号并将RF信号提供给调谐器的多个信道的分离器。 每个通道可以包括用于放大RF信号的放大器，使用本地振荡器（LO）信号将放大的RF信号下变频到第二频率信号的混频器，其中每个信道被配置为接收不同的LO信号，滤波器 对下变频的第二频率信号进行滤波，以及数字转换器，对下变频的第二频率信号进行数字化。 时钟发生电路具有多个内插分频器和频率合成器，以产生参考时钟信号。 每个内插分频器被配置为接收参考时钟信号，产生相应的LO信号，并将相应的LO信号提供给至少一个信道的混频器。