公开(公告)号：US20220334960A1

公开(公告)日：2022-10-20

申请号：US17853888

申请日：2022-06-29

Applicant: Silicon Motion, Inc.

Inventor： Jian-Dong Du ,  Chia-Jung Hsiao ,  Pi-Ju Tsai

IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4074 ,  G06F11/07

Abstract: A flash memory controller includes a read only memory (ROM) and a microprocessor. The ROM is arranged to store a program code. The microprocessor is arranged to execute the program code to control access of a flash memory module. When executing the program code, the microprocessor is arranged to perform operations of: monitoring data retention state of one or more blocks in the flash memory module by reading a last page of the one or more blocks to obtain time information regarding the one or more blocks, which is generated by the flash memory controller; and arranging a specific block to a garbage collection process if time information obtained from the last page of the specific block exceeds a threshold.

公开(公告)号：US20210318953A1

公开(公告)日：2021-10-14

申请号：US17355192

申请日：2021-06-23

Applicant: Silicon Motion, Inc.

Inventor： Jian-Dong Du ,  Chia-Jung Hsiao ,  Tsung-Chieh Yang

IPC: G06F12/02 ,  G06F12/0882 ,  G11C11/4093 ,  G11C11/4099 ,  G11C11/4074 ,  G06F13/16

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.

公开(公告)号：US20200310648A1

公开(公告)日：2020-10-01

申请号：US16735709

申请日：2020-01-07

Applicant: Silicon Motion, Inc.

Inventor： Jian-Dong Du ,  Chia-Jung Hsiao ,  Tsung-Chieh Yang

IPC: G06F3/06 ,  G06F12/02

Abstract: A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.

公开(公告)号：US20200225876A1

公开(公告)日：2020-07-16

申请号：US16732333

申请日：2020-01-01

Applicant: Silicon Motion, Inc.

Inventor： Jian-Dong Du ,  Pi-Ju Tsai ,  Tsung-Chieh Yang

IPC: G06F3/06 ,  G06F11/07

Abstract: The present invention proposes a method for managing a plurality of memory units in a flash memory module. The method includes: creating a programed timestamp corresponding to each first memory unit according to a data-written time of said each first memory unit; selecting a corresponding read-retry table for performing a read operation upon said each first memory unit according to the programed timestamp of said each first memory unit; and performing a first refresh operation according to program timestamps of first memory units that have been written with data.

公开(公告)号：US10164656B2

公开(公告)日：2018-12-25

申请号：US15086006

申请日：2016-03-30

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Jian-Dong Du

IPC: H03M13/11 ,  H03M13/37 ,  H03M13/45

Abstract: A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.

公开(公告)号：US10019314B2

公开(公告)日：2018-07-10

申请号：US15874895

申请日：2018-01-19

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu ,  Jian-Dong Du

IPC: G11C16/04 ,  G06F11/10 ,  G11C29/52 ,  G11C11/56 ,  G11C16/26 ,  G11C16/10

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A method used for a flash memory module having a plurality of storage blocks each can be used as a first block or a second block includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks; reading out the groups of data from the first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon the randomized data to generate a second corresponding parity check code; and storing the randomized data and the second corresponding parity check code into the flash memory module as the second block.