公开(公告)号：US20200035310A1

公开(公告)日：2020-01-30

申请号：US16590798

申请日：2019-10-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C11/54 ,  G11C16/04 ,  G06N3/08 ,  G11C16/30 ,  G11C16/26

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.

公开(公告)号：US20200019849A1

公开(公告)日：2020-01-16

申请号：US16151259

申请日：2018-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Thuan Vu ,  Anh Ly ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/063 ,  G06F3/06 ,  G06F11/16

Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

公开(公告)号：US10534554B2

公开(公告)日：2020-01-14

申请号：US15784025

申请日：2017-10-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  H01L21/78 ,  H01L27/11521 ,  H01L29/423 ,  H01L23/00

Abstract: Apparatus, and an associated method, for enhancing security and preventing hacking of a flash memory device. The apparatus and method use a random number to offset the read or write address in a memory cell. The random number is generated by determining the leakage current of memory cells. In another embodiment, random data can be written or read in parallel to thwart hackers from determining contents of data being written or read by monitoring sense amplifiers.

公开(公告)号：US20190355420A1

公开(公告)日：2019-11-21

申请号：US16526987

申请日：2019-07-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C16/04 ,  G11C16/28

Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.

公开(公告)号：US20190341110A1

公开(公告)日：2019-11-07

申请号：US16042972

申请日：2018-07-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Staniey Hong ,  Anh Ly ,  Vlpln Tlwarl ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L29/788 ,  H01L27/11521

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US10460811B2

公开(公告)日：2019-10-29

申请号：US16387377

申请日：2019-04-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/04

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US20190206486A1

公开(公告)日：2019-07-04

申请号：US16213860

申请日：2018-12-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C2211/5641

Abstract: A memory device includes memory cells each configured to produce an output current during a read operation. Circuitry is configured to, for each of the memory cells, generate a read value based on the output current of the memory cell. Circuitry is configured to, for each of the memory cells, multiply the read value for the memory cell by a multiplier to generate a multiplied read value, wherein the multiplier for each of the memory cells is different from the multipliers for any others of the memory cells. Circuitry is configured to sum the multiplied read values. The read values can be electrical currents, electrical voltages or numerical values. Alternatively, added constant values can be used instead of multipliers. The multipliers or constants can be applied to read currents from individual cells, or read currents on entire bit lines.

公开(公告)号：US10340010B2

公开(公告)日：2019-07-02

申请号：US15238681

申请日：2016-08-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/32

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

公开(公告)号：US10325666B2

公开(公告)日：2019-06-18

申请号：US16218398

申请日：2018-12-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C7/00 ,  G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11521 ,  G11C16/26 ,  G11C5/14 ,  G11C16/10 ,  G11C8/08 ,  G11C16/16

Abstract: During a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.

公开(公告)号：US20190172543A1

公开(公告)日：2019-06-06

申请号：US16271673

申请日：2019-02-08

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/34 ,  H01L27/11524 ,  H01L29/788 ,  G11C16/04 ,  G11C8/14 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/14 ,  G11C16/10 ,  H01L27/11558 ,  G11C7/18

CPC classification number: G11C16/3431 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558 ,  H01L29/7881

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.