公开(公告)号：US10312247B1

公开(公告)日：2019-06-04

申请号：US15933124

申请日：2018-03-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/11524 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28

Abstract: A non-volatile memory cell formed on a semiconductor substrate having an upper surface with an upwardly extending fin with opposing first and second side surfaces. First and second electrodes are in electrical contact with first and second portions of the fin. A channel region of the fin includes portions of the first and second side surfaces that extend between the first and second portions of the fin. A floating gate extends along the first side surface of a first portion of the channel region, where no portion of the floating gate extends along the second side surface. A word line gate extends along the first and second side surfaces of a second portion of the channel region. A control gate is disposed over the floating gate. An erase gate has a first portion disposed laterally adjacent to the floating gate and a second portion disposed vertically over the floating gate.

公开(公告)号：US09673208B2

公开(公告)日：2017-06-06

申请号：US15264457

申请日：2016-09-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Chien-Sheng Su ,  Feng Zhou ,  Xian Liu ,  Nhan Do ,  Prateep Tuntasood ,  Parviz Ghazavi

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/11531

CPC classification number: H01L27/11531 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.

公开(公告)号：US20150325300A1

公开(公告)日：2015-11-12

申请号：US14275362

申请日：2014-05-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Anh Ly ,  Victor Markov

IPC: G11C16/14 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/3427

Abstract: An improved control gate decoding design for reducing disturbances during the programming of flash memory cells is disclosed. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector.

Abstract translation: 公开了一种改进的控制门解码设计，用于在闪速存储器单元的编程期间减少干扰。 在一个实施例中，控制栅极线解码器耦合到与第一扇区中的一行闪存单元相关联的第一控制栅极线和耦合到与第二扇区中的一行闪存单元相关联的第二控制栅极线。