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公开(公告)号：US07414917B2
公开(公告)日：2008-08-19
申请号：US11192335
申请日：2005-07-29
IPC分类号： G11C8/00
摘要： Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.
摘要翻译： 本文描述了使用其的半导体存储器模块和半导体存储器系统。 这些模块将常规DIMM分成一系列独立的较小内存模块。 每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。 在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。
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32.发明授权Semiconductor memory device including a signal control device and method of operating the same 有权包括信号控制装置的半导体存储装置及其操作方法公开(公告)号：US07404136B2
公开(公告)日：2008-07-22
申请号：US11182063
申请日：2005-07-15
IPC分类号： H03M13/00
CPC分类号： G11C7/1006 , G06F11/1052 , G11C29/42 , G11C2207/104
摘要： A semiconductor memory device including semiconductor memory cells with at least one memory cell capable of either acting as a storage device for ECC information or of acting as a redundant memory cell is provided. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either as a storage device or as a redundant memory cell. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either as a storing device for ECC information or as a redundant memory cell.
摘要翻译： 提供一种半导体存储器件，其包括具有至少一个存储单元的半导体存储单元，所述至少一个存储单元可以充当用于ECC信息的存储器件或用作冗余存储器单元。 半导体存储器件还包括信号控制装置，用于发信号通知至少一个存储单元是作为存储装置还是用作冗余存储单元。 还提供了一种操作半导体存储器件的方法，包括以下步骤：注册信号器件的状态，并且根据信号器件的状态，操作至少一个存储器单元作为ECC信息的存储设备或者作为 冗余存储单元。
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公开(公告)号：US07386696B2
公开(公告)日：2008-06-10
申请号：US10887019
申请日：2004-07-08
IPC分类号： G06F12/00
CPC分类号： G11C5/063
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.
摘要翻译： 本发明涉及一种半导体存储器模块，其具有布置在至少一行的多个存储器芯片和至少一个缓冲器芯片，该缓冲器芯片驱动并接收时钟信号，以及将命令和寻址信号存储到存储器芯片以及从存储器芯片传送数据信号 通过模块内的时钟，地址，命令和数据总线，并形成与外部主存储器总线的接口。 半导体存储器模块具有布置在其上的偶数个缓冲器芯片，并且所有存储器芯片至少通过一个信号线类型从信号组连接到两个相应的缓冲器芯片，并且仅剩下两个缓冲器芯片之一 来自该组的信号线。 在读取操作期间，通过其线从一个缓冲芯片到相应的一个存储器芯片的致动信号的电信号传播时间和从该存储器芯片到另一个缓冲器芯片的数据信号的电信号传播时间之和 对于所有存储器芯片是相同的，并且提供用于控制到存储器芯片或从存储器芯片的相应数据写入和读取操作的控制装置，以便以与数据相同的相同方向驱动时钟信号和命令和寻址信号 当数据被写入和读取时通过模块内的总线发送信号。
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公开(公告)号：US20070263425A1
公开(公告)日：2007-11-15
申请号：US11672778
申请日：2007-02-08
申请人： Hermann Ruckerbauer
发明人： Hermann Ruckerbauer
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , H01L2224/16227 , H01L2224/32145 , H01L2224/48147 , H01L2224/48227 , H01L2224/49113 , H01L2224/73265 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： A memory arrangement is disclosed. In one embodiment, the control device includes a plurality of memory arrays for storing data and a control device for controlling the transfer of data between the plurality of memory arrays and external circuits. In one embodiment, the control device is arranged on a different semiconductor chip than the plurality of memory arrays. The plurality of memory arrays is arranged symmetrically in a plurality of stacks and the control device is arranged in a central arrangement with respect to the stacks.
摘要翻译： 公开了存储装置。 在一个实施例中，控制装置包括用于存储数据的多个存储器阵列和用于控制多个存储器阵列和外部电路之间的数据传送的控制装置。 在一个实施例中，控制装置布置在与多个存储器阵列不同的半导体芯片上。 多个存储器阵列对称地布置在多个堆叠中，并且控制装置相对于堆叠布置成中心布置。
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公开(公告)号：US07293151B2
公开(公告)日：2007-11-06
申请号：US10872427
申请日：2004-06-22
申请人： Hermann Ruckerbauer
发明人： Hermann Ruckerbauer
IPC分类号： G06F12/00
CPC分类号： G11C7/1018 , G06F13/1684
摘要： A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.
摘要翻译： 存储器系统在功能上被设计成使得尽管在没有纠错装置的情况下进行操作，但实际提供用于纠错的存储器模块的存储器芯片被同时用于数据传输。 控制装置被配置为接收，存储和传送数据分组到第一和第二组存储器芯片。 将内部分组数据从控制设备传送到存储器进行，使得第一记录被存储在第二组存储器芯片中，并且附加记录被存储在第一组存储器芯片中。 在优选实施例中，在第二组存储器芯片中分配数据，使得与传送到第一组存储器芯片相比，至少一个额外的转移步骤发生到第二组存储器芯片。 在附加传送步骤中，第一组存储器芯片被从接收数据中被掩蔽。
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公开(公告)号：US20070246257A1
公开(公告)日：2007-10-25
申请号：US11737108
申请日：2007-04-18
申请人： Simon Muff , Hermann Ruckerbauer
发明人： Simon Muff , Hermann Ruckerbauer
IPC分类号： H05K7/02
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , H01L25/0652 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2225/06586 , H01L2924/0102 , H01L2924/01068 , H01L2924/01078 , H01L2924/15182 , H01L2924/15311 , H01L2924/00014
摘要： A memory circuit includes multiple memory chips configured to store data and disposed in at least one stack. The memory circuit includes multiple ports configured to receive and transmit control signals and data to and from the memory chips and to supply energy to the memory circuit. The memory circuit includes a housing accommodating the multiple memory chips and the multiple ports.
摘要翻译： 存储器电路包括被配置为存储数据并设置在至少一个堆叠中的多个存储器芯片。 存储器电路包括多个端口，其被配置为从存储器芯片接收和发送控制信号和数据，并向存储器电路提供能量。 存储器电路包括容纳多个存储器芯片和多个端口的壳体。
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公开(公告)号：US07224636B2
公开(公告)日：2007-05-29
申请号：US10890934
申请日：2004-07-14
IPC分类号： G11C8/00
CPC分类号： G11C29/028 , G11C5/063 , G11C29/50012
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.
摘要翻译： 本发明涉及一种半导体存储器模块，该半导体存储器模块具有彼此排成一列的多个存储器芯片。 存储器模块具有模块内部时钟，命令/地址和数据总线，其将时钟信号，命令和地址信号以及数据信号从存储器控制器设备传送到存储器芯片，并将数据信号从存储器芯片传送到存储器控制器设备 。 存储器模块具有各自的时钟，命令/地址和数据信号线。 时钟信号线包括两个差分时钟信号线，它们在其与存储器控制器装置相对的端部通过短路桥断开或彼此连接。 在写入操作期间，存储器芯片将写入数据与从存储器控制器设备运行到时钟信号线的时钟信号同步，并且在读取操作期间，与从该存储器控制器设备反射的时钟信号同步地输出读取数据 开路或短路的时钟信号线。
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公开(公告)号：US20070058408A1
公开(公告)日：2007-03-15
申请号：US11226447
申请日：2005-09-15
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G06F13/1668
摘要： A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.
摘要翻译： 一种用于在具有用于存储用户数据的至少一个半导体存储器芯片和用于控制至少一个半导体存储器芯片的一个存储器控制器的数据存储系统中操作的半导体存储器阵列包括至少一个用于控制的单向串行信号线总线 以及与存储器控制器连接的地址信号，将至少一个半导体存储器芯片与存储器控制器直接连接，并且通过1点到1点连接彼此串联连接半导体存储器芯片。
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39.发明授权Memory device, memory controller and memory system having bidirectional clock lines 有权存储器件，存储器控制器和具有双向时钟线的存储器系统公开(公告)号：US07180821B2
公开(公告)日：2007-02-20
申请号：US10954869
申请日：2004-09-30
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C5/04 , G11C7/22 , G11C7/225
摘要： One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.
摘要翻译： 本发明的一个实施例提供了一种适于根据写时钟信号接收数据并根据读时钟信号输出数据的存储器件，包括配置成输出读时钟信号并接收写时钟信号的时钟端口 以及串行双向驱动器，被配置为经由时钟端口输出读取时钟信号，并经由时钟端口同时接收写时钟信号。
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公开(公告)号：US20060155948A1
公开(公告)日：2006-07-13
申请号：US11259452
申请日：2005-10-26
申请人： Hermann Ruckerbauer
发明人： Hermann Ruckerbauer
IPC分类号： G06F13/28
CPC分类号： G11C7/1051 , G11C7/1066
摘要： A semiconductor memory system is proposed, in which the transmission of memory data of a burst that follows command/address data of a write/read command is identified by means of a modified clock signal. The modified clock signal has identifying regions with masked-out clock edges, so that the transmission of memory data can be signalled with the clock edge following the identifying regions.
摘要翻译： 提出了一种半导体存储器系统，其中通过修改的时钟信号来识别遵循写入/读取命令的命令/地址数据的突发的存储器数据的传输。 经修改的时钟信号具有被掩蔽的时钟边缘的识别区域，使得存储器数据的传输可以用跟随识别区域的时钟边沿来发信号通知。
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