利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

126 条记录 (耗时 0.05 秒)

    Method of forming wiring of a semiconductor memory device
    33.
    发明授权
    Method of forming wiring of a semiconductor memory device 有权
    形成半导体存储器件布线的方法

    公开(公告)号：US07642187B2

    公开(公告)日：2010-01-05

    申请号：US11905397

    申请日：2007-09-28

    申请人： Sang-Hyun Lee ,  Min-Soo Kim ,  Tae-Hoon Kim

    发明人： Sang-Hyun Lee ,  Min-Soo Kim ,  Tae-Hoon Kim

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76838 ,  H01L21/32051 ,  H01L27/10894 ,  H01L27/10897

    摘要： A method of forming a wiring for a semiconductor memory device includes obtaining a semiconductor substrate, depositing at least one conductive layer on the semiconductor substrate under controlled conditions, such as substrate temperature and atmosphere temperature, to provide a conductive layer exhibiting a reduced surface roughness as compared to a comparable conductive layer deposited under uncontrolled conditions, and patterning the conductive layer to form a wiring.

    摘要翻译： 一种形成半导体存储器件布线的方法包括获得半导体衬底，在诸如衬底温度和气氛温度的受控条件下在半导体衬底上沉积至少一个导电层，以提供具有降低的表面粗糙度的导电层， 与在不受控制的条件下沉积的可比导电层相比，并且图案化导电层以形成布线。

    Flat panel display device
    34.
    发明申请
    Flat panel display device 有权
    平板显示设备

    公开(公告)号：US20090201635A1

    公开(公告)日：2009-08-13

    申请号：US12320885

    申请日：2009-02-06

    申请人： Min-Cheol Kim ,  Gil-Jae Choi ,  Sang-Hyun Lee

    发明人： Min-Cheol Kim ,  Gil-Jae Choi ,  Sang-Hyun Lee

    IPC分类号： H05K5/02

    CPC分类号： H01L51/0097 ,  G02F1/133308 ,  G02F2001/133314 ,  G02F2001/13332 ,  G02F2201/503 ,  Y02E10/549 ,  Y02P70/521

    摘要： A flat panel display device includes a bezel and a flat display panel accommodated in the bezel. The bezel includes a substrate part, bent parts, each of which is formed on one of edges of the substrate part and extends substantially perpendicular to the substrate part, and a protrusion formed at an end of one of the bent parts. In another embodiment, a flat panel display device further includes a cover bezel covering the bezel and the flat display panel. The cover bezel has an open window through which light from the flat panel display transmits, and the cover bezel includes an insertion part that is coupled with the protrusion.

    摘要翻译： 平板显示装置包括一个挡板和一个容纳在挡板中的平板显示面板。 所述边框包括基板部分，弯曲部分，每个弯曲部分形成在所述基板部分的一个边缘上并且基本上垂直于所述基板部分延伸，以及形成在所述弯曲部分之一的端部处的突起。 在另一个实施例中，平板显示装置还包括覆盖边框和平板显示面板的盖边框。 盖边框具有开放的窗口，来自平板显示器的光通过该窗口传播，并且盖边框包括与突起联接的插入部分。

    Method of manufacturing field emitter
    35.
    发明授权
    Method of manufacturing field emitter 失效
    制造场发射体的方法

    公开(公告)号：US07507135B2

    公开(公告)日：2009-03-24

    申请号：US11048809

    申请日：2005-02-03

    申请人： Sang-Hyun Lee ,  Jeong-Hee Lee ,  Shang-Hyeun Park ,  Tae-Won Jeong ,  Jung-Na Heo ,  Won-Seok Kim

    发明人： Sang-Hyun Lee ,  Jeong-Hee Lee ,  Shang-Hyeun Park ,  Tae-Won Jeong ,  Jung-Na Heo ,  Won-Seok Kim

    IPC分类号： H01J9/00

    CPC分类号： H01J9/025 ,  B82Y10/00 ,  H01J1/304 ,  H01J2201/30469

    摘要： In a method of manufacturing a field emitter, a patterned conductive layer is formed on a substrate, an upper surface of the conductive layer is coated with a mixture of a field emission material and metal powder, the mixture is thermally treated to improve adhesion of the mixture to the conductive layer, and a field emission material and a metal deposited on a portion of the substrate other than the conductive layer are removed. Accordingly, the lifespan and field emission characteristic of the field emitter are greatly improved, and a large area field emitter having excellent characteristics that cannot be realized in the conventional art is fabricated.

    摘要翻译： 在制造场致发射体的方法中，在基板上形成图案化的导电层，用场致发射材料和金属粉末的混合物涂覆导电层的上表面，对该混合物进行热处理以提高 混合物到导电层，并且除去导电层之外的场致发射材料和沉积在基板的一部分上的金属。 因此，场致发射体的寿命和场发射特性大大提高，并且制造了在现有技术中无法实现的具有优异特性的大面积场致发射体。

    Method of manufacturing nano-wire
    36.
    发明授权
    Method of manufacturing nano-wire 失效
    制造纳米线的方法

    公开(公告)号：US07393410B2

    公开(公告)日：2008-07-01

    申请号：US11114196

    申请日：2005-04-26

    申请人： Sang-Hyun Lee ,  Tae-Won Jeong ,  Jeong-Na Huh

    发明人： Sang-Hyun Lee ,  Tae-Won Jeong ,  Jeong-Na Huh

    IPC分类号： C30B25/00 ,  C30B29/66

    CPC分类号： C30B25/18 ,  C30B25/02 ,  C30B29/605 ,  Y10S977/813 ,  Y10S977/814 ,  Y10S977/825

    摘要： There is provided a method of manufacturing a nano-wire using a crystal structure. In the method of manufacturing a nano-wire, a crystal grain having a plurality of crystal faces is used as a seed, and a crystal growing material having a lattice constant difference within a predetermined range is deposited on the crystal grain, thereby allowing the nano-wire to grow from at least one of the crystal faces. Therefore, it is possible to give the positional selectivity with a simple process using a principle of crystal growth and to generate a nano-structure such as a nano-wire, etc. having good crystallinity. Further, it is possible to generate a different-kind junction structure having various shapes by adjusting a feature of a crystal used as a seed.

    摘要翻译： 提供了使用晶体结构制造纳米线的方法。 在制造纳米线的方法中，使用具有多个晶面的晶粒作为种子，并且在晶粒上沉积具有规定范围内的晶格常数差的晶体生长材料，由此使纳米线 从至少一个晶面生长。 因此，可以通过使用晶体生长原理的简单工艺来产生位置选择性，并且可以产生具有良好结晶度的纳米线等纳米结构。 此外，通过调整用作种子的晶体的特征，可以生成具有各种形状的不同种类的连接结构。

    Method of forming asymmetric MOS transistor with a channel stopping region and a trench-type gate
    37.
    发明授权
    Method of forming asymmetric MOS transistor with a channel stopping region and a trench-type gate 有权
    形成具有通道停止区域的非对称MOS晶体管和沟槽型栅极的方法

    公开(公告)号：US07378320B2

    公开(公告)日：2008-05-27

    申请号：US11021349

    申请日：2004-12-23

    申请人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

    发明人： Hyeoung-Won Seo ,  Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659

    摘要： A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.

    摘要翻译： 制造具有沟槽型栅极的MOS（金属氧化物半导体）晶体管，其具有沟道停止区域，用于形成用于减小短沟道效应的不对称沟道区域。 例如在制造N沟道MOS晶体管时，栅极结构形成在P阱内的沟槽内。 在沟槽的第一侧形成具有P型掺杂剂的沟道停止区，以在其中完全包含N型源极结。 在LDD区内形成N型漏极结至沟槽的第二侧，从而形成非对称沟道区。

    High-voltage electric double layer capacitor
    38.
    发明授权
    High-voltage electric double layer capacitor 有权
    高压双电层电容器

    公开(公告)号：US07145763B2

    公开(公告)日：2006-12-05

    申请号：US11240373

    申请日：2005-10-03

    申请人： Yu-Tack Kim ,  Moon-Bae Lee ,  Sang-Hyun Lee ,  Sang-Ick Lee ,  Chul-Wan Park ,  Jin-Bae Park ,  Kwang-Chul Roh ,  Jin-Hyoung Son ,  Seung-Hwan Song

    发明人： Yu-Tack Kim ,  Moon-Bae Lee ,  Sang-Hyun Lee ,  Sang-Ick Lee ,  Chul-Wan Park ,  Jin-Bae Park ,  Kwang-Chul Roh ,  Jin-Hyoung Son ,  Seung-Hwan Song

    IPC分类号： H01G9/00 ,  H01G9/02

    CPC分类号： H01G9/155 ,  H01G9/151 ,  Y02E60/13

    摘要： The present invention relates to a high-voltage electric double layer capacitor (EDLC), and more particularly, to an EDLC in which a surge voltage and an operating voltage are enhanced by improving the structure of a unit cell. The EDLC according to the present invention includes a unit cell having at least three electrodes. According to a preferred embodiment of the present invention, the unit cell has a structure constructed by sequentially laminating a first insulating paper layer with a sheet of insulating paper, a first electrode layer with at least two electrodes, a second insulating paper layer with a sheet of insulating paper, and a second electrode layer with at least one electrode. In accordance with the present invention, the number of electrode-facing surfaces increases, and a surge voltage and an operating voltage increase in proportion to the increased number of the electrode-facing surfaces, resulting in a high energy storage density. Accordingly, the present invention has advantages in that an EDLC with a single cell can be applied to products, an EDLC module can be miniaturized, and there is no need for a protection circuit for maintaining voltage balance on a unit cell basis upon fabrication of the module.

    摘要翻译： 高电压双层电容器（EDLC）技术领域本发明涉及一种高压双电层电容器（EDLC），更具体地说，涉及一种通过改善晶胞结构来提高浪涌电压和工作电压的EDLC。 根据本发明的EDLC包括具有至少三个电极的单元电池。 根据本发明的优选实施例，单元电池具有通过依次层叠第一绝缘纸层与绝缘纸片，具有至少两个电极的第一电极层，具有片材的第二绝缘纸层而构成的结构 的绝缘纸，以及具有至少一个电极的第二电极层。 根据本发明，面向电极的表面的数量增加，并且浪涌电压和工作电压与增加的电极面对表面的数量成比例地增加，导致高的储能密度。 因此，本发明的优点在于，具有单个电池的EDLC可以应用于产品，EDLC模块可以被小型化，并且不需要保护电路，用于在制造基于单元的基础上保持基于单元电池的电压平衡 模块。

    HIGH-VOLTAGE ELECTRIC DOUBLE LAYER CAPACITOR
    40.
    发明申请
    HIGH-VOLTAGE ELECTRIC DOUBLE LAYER CAPACITOR 有权
    高压双电层电容器

    公开(公告)号：US20060221551A1

    公开(公告)日：2006-10-05

    申请号：US11240373

    申请日：2005-10-03

    申请人： Yu-Tack Kim ,  Jin-Hyoung Son ,  Moon-Bae Lee ,  Sang-Hyun Lee ,  Kwang-Chul Roh ,  Seung-Hwan Song ,  Chul-Wan Park ,  Sang-Ick Lee ,  Jin-Bae Park

    发明人： Yu-Tack Kim ,  Jin-Hyoung Son ,  Moon-Bae Lee ,  Sang-Hyun Lee ,  Kwang-Chul Roh ,  Seung-Hwan Song ,  Chul-Wan Park ,  Sang-Ick Lee ,  Jin-Bae Park

    IPC分类号： H01G9/00

    CPC分类号： H01G9/155 ,  H01G9/151 ,  Y02E60/13

    摘要： The present invention relates to a high-voltage electric double layer capacitor (EDLC), and more particularly, to an EDLC in which a surge voltage and an operating voltage are enhanced by improving the structure of a unit cell. The EDLC according to the present invention includes a unit cell having at least three electrodes. According to a preferred embodiment of the present invention, the unit cell has a structure constructed by sequentially laminating a first insulating paper layer with a sheet of insulating paper, a first electrode layer with at least two electrodes, a second insulating paper layer with a sheet of insulating paper, and a second electrode layer with at least one electrode. In accordance with the present invention, the number of electrode-facing surfaces increases, and a surge voltage and an operating voltage increase in proportion to the increased number of the electrode-facing surfaces, resulting in a high energy storage density. Accordingly, the present invention has advantages in that an EDLC with a single cell can be applied to products, an EDLC module can be miniaturized, and there is no need for a protection circuit for maintaining voltage balance on a unit cell basis upon fabrication of the module.

    摘要翻译： 高电压双层电容器（EDLC）技术领域本发明涉及一种高压双电层电容器（EDLC），更具体地说，涉及一种通过改善晶胞结构来提高浪涌电压和工作电压的EDLC。 根据本发明的EDLC包括具有至少三个电极的单元电池。 根据本发明的优选实施例，单元电池具有通过依次层叠第一绝缘纸层与绝缘纸片，具有至少两个电极的第一电极层，具有片材的第二绝缘纸层而构成的结构 的绝缘纸，以及具有至少一个电极的第二电极层。 根据本发明，面向电极的表面的数量增加，并且浪涌电压和工作电压与增加的电极面对表面的数量成比例地增加，导致高的储能密度。 因此，本发明的优点在于，具有单个电池的EDLC可以应用于产品，EDLC模块可以被小型化，并且不需要保护电路，用于在制造基于单元的基础上维持基于单元电池的电压平衡 模块。